📄 any_div.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "39 " "Warning: Found 39 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cnt1\[28\] " "Info: Detected ripple clock \"cnt1\[28\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[28\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[26\] " "Info: Detected ripple clock \"cnt1\[26\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[26\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[25\] " "Info: Detected ripple clock \"cnt1\[25\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[25\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[27\] " "Info: Detected ripple clock \"cnt1\[27\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[27\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[12\] " "Info: Detected ripple clock \"cnt1\[12\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[12\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[11\] " "Info: Detected ripple clock \"cnt1\[11\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[11\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[14\] " "Info: Detected ripple clock \"cnt1\[14\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[14\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[13\] " "Info: Detected ripple clock \"cnt1\[13\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[13\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[17\] " "Info: Detected ripple clock \"cnt1\[17\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[17\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[15\] " "Info: Detected ripple clock \"cnt1\[15\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[15\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[16\] " "Info: Detected ripple clock \"cnt1\[16\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[16\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[18\] " "Info: Detected ripple clock \"cnt1\[18\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[18\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[20\] " "Info: Detected ripple clock \"cnt1\[20\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[20\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[21\] " "Info: Detected ripple clock \"cnt1\[21\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[21\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[22\] " "Info: Detected ripple clock \"cnt1\[22\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[22\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[19\] " "Info: Detected ripple clock \"cnt1\[19\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[19\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[10\] " "Info: Detected ripple clock \"cnt1\[10\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[10\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[7\] " "Info: Detected ripple clock \"cnt1\[7\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[7\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[9\] " "Info: Detected ripple clock \"cnt1\[9\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[9\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[8\] " "Info: Detected ripple clock \"cnt1\[8\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[8\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[6\] " "Info: Detected ripple clock \"cnt1\[6\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[6\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[5\] " "Info: Detected ripple clock \"cnt1\[5\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[4\] " "Info: Detected ripple clock \"cnt1\[4\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[3\] " "Info: Detected ripple clock \"cnt1\[3\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[2\] " "Info: Detected ripple clock \"cnt1\[2\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[0\] " "Info: Detected ripple clock \"cnt1\[0\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[23\] " "Info: Detected ripple clock \"cnt1\[23\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[23\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[24\] " "Info: Detected ripple clock \"cnt1\[24\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[24\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[31\] " "Info: Detected ripple clock \"cnt1\[31\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[31\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~342 " "Info: Detected gated clock \"Equal0~342\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~342" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[30\] " "Info: Detected ripple clock \"cnt1\[30\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[30\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[29\] " "Info: Detected ripple clock \"cnt1\[29\]\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[29\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~337 " "Info: Detected gated clock \"Equal0~337\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~337" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~336 " "Info: Detected gated clock \"Equal0~336\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~336" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~335 " "Info: Detected gated clock \"Equal0~335\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~335" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~338 " "Info: Detected gated clock \"Equal0~338\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~338" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~340 " "Info: Detected gated clock \"Equal0~340\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~340" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~341 " "Info: Detected gated clock \"Equal0~341\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~341" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~343 " "Info: Detected gated clock \"Equal0~343\" as buffer" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~343" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register cnt1\[0\] register cnt1\[31\] 5.492 ns " "Info: Slack time is 5.492 ns for clock \"clk\" between source register \"cnt1\[0\]\" and destination register \"cnt1\[31\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "221.83 MHz 4.508 ns " "Info: Fmax is 221.83 MHz (period= 4.508 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.787 ns + Largest register register " "Info: + Largest register to register requirement is 9.787 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 10.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 10.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 10.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns + Largest " "Info: + Largest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.373 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.537 ns) 2.373 ns cnt1\[31\] 3 REG LCFF_X21_Y11_N31 2 " "Info: 3: + IC(0.725 ns) + CELL(0.537 ns) = 2.373 ns; Loc. = LCFF_X21_Y11_N31; Fanout = 2; REG Node = 'cnt1\[31\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.262 ns" { clk~clkctrl cnt1[31] } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.31 % ) " "Info: Total cell delay = 1.526 ns ( 64.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.847 ns ( 35.69 % ) " "Info: Total interconnect delay = 0.847 ns ( 35.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.373 ns" { clk clk~clkctrl cnt1[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.373 ns" { clk clk~combout clk~clkctrl cnt1[31] } { 0.000ns 0.000ns 0.122ns 0.725ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.372 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.537 ns) 2.372 ns cnt1\[0\] 3 REG LCFF_X20_Y11_N17 3 " "Info: 3: + IC(0.724 ns) + CELL(0.537 ns) = 2.372 ns; Loc. = LCFF_X20_Y11_N17; Fanout = 3; REG Node = 'cnt1\[0\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.261 ns" { clk~clkctrl cnt1[0] } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.33 % ) " "Info: Total cell delay = 1.526 ns ( 64.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.846 ns ( 35.67 % ) " "Info: Total interconnect delay = 0.846 ns ( 35.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.372 ns" { clk clk~clkctrl cnt1[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.372 ns" { clk clk~combout clk~clkctrl cnt1[0] } { 0.000ns 0.000ns 0.122ns 0.724ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.373 ns" { clk clk~clkctrl cnt1[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.373 ns" { clk clk~combout clk~clkctrl cnt1[31] } { 0.000ns 0.000ns 0.122ns 0.725ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.372 ns" { clk clk~clkctrl cnt1[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.372 ns" { clk clk~combout clk~clkctrl cnt1[0] } { 0.000ns 0.000ns 0.122ns 0.724ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.373 ns" { clk clk~clkctrl cnt1[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.373 ns" { clk clk~combout clk~clkctrl cnt1[31] } { 0.000ns 0.000ns 0.122ns 0.725ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.372 ns" { clk clk~clkctrl cnt1[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.372 ns" { clk clk~combout clk~clkctrl cnt1[0] } { 0.000ns 0.000ns 0.122ns 0.724ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.295 ns - Longest register register " "Info: - Longest register to register delay is 4.295 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt1\[0\] 1 REG LCFF_X20_Y11_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y11_N17; Fanout = 3; REG Node = 'cnt1\[0\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt1[0] } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.393 ns) 1.420 ns Add0~385 2 COMB LCCOMB_X21_Y12_N0 2 " "Info: 2: + IC(1.027 ns) + CELL(0.393 ns) = 1.420 ns; Loc. = LCCOMB_X21_Y12_N0; Fanout = 2; COMB Node = 'Add0~385'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.420 ns" { cnt1[0] Add0~385 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.491 ns Add0~387 3 COMB LCCOMB_X21_Y12_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.491 ns; Loc. = LCCOMB_X21_Y12_N2; Fanout = 2; COMB Node = 'Add0~387'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~385 Add0~387 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.562 ns Add0~389 4 COMB LCCOMB_X21_Y12_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.562 ns; Loc. = LCCOMB_X21_Y12_N4; Fanout = 2; COMB Node = 'Add0~389'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~387 Add0~389 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.633 ns Add0~391 5 COMB LCCOMB_X21_Y12_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.633 ns; Loc. = LCCOMB_X21_Y12_N6; Fanout = 2; COMB Node = 'Add0~391'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~389 Add0~391 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.704 ns Add0~393 6 COMB LCCOMB_X21_Y12_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.704 ns; Loc. = LCCOMB_X21_Y12_N8; Fanout = 2; COMB Node = 'Add0~393'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~391 Add0~393 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.775 ns Add0~395 7 COMB LCCOMB_X21_Y12_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.775 ns; Loc. = LCCOMB_X21_Y12_N10; Fanout = 2; COMB Node = 'Add0~395'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~393 Add0~395 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.846 ns Add0~397 8 COMB LCCOMB_X21_Y12_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.846 ns; Loc. = LCCOMB_X21_Y12_N12; Fanout = 2; COMB Node = 'Add0~397'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~395 Add0~397 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.005 ns Add0~399 9 COMB LCCOMB_X21_Y12_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 2.005 ns; Loc. = LCCOMB_X21_Y12_N14; Fanout = 2; COMB Node = 'Add0~399'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~397 Add0~399 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.076 ns Add0~401 10 COMB LCCOMB_X21_Y12_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 2.076 ns; Loc. = LCCOMB_X21_Y12_N16; Fanout = 2; COMB Node = 'Add0~401'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~399 Add0~401 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.147 ns Add0~403 11 COMB LCCOMB_X21_Y12_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 2.147 ns; Loc. = LCCOMB_X21_Y12_N18; Fanout = 2; COMB Node = 'Add0~403'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~401 Add0~403 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.218 ns Add0~405 12 COMB LCCOMB_X21_Y12_N20 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 2.218 ns; Loc. = LCCOMB_X21_Y12_N20; Fanout = 2; COMB Node = 'Add0~405'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~403 Add0~405 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.289 ns Add0~407 13 COMB LCCOMB_X21_Y12_N22 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 2.289 ns; Loc. = LCCOMB_X21_Y12_N22; Fanout = 2; COMB Node = 'Add0~407'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~405 Add0~407 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.360 ns Add0~409 14 COMB LCCOMB_X21_Y12_N24 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 2.360 ns; Loc. = LCCOMB_X21_Y12_N24; Fanout = 2; COMB Node = 'Add0~409'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~407 Add0~409 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.431 ns Add0~411 15 COMB LCCOMB_X21_Y12_N26 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 2.431 ns; Loc. = LCCOMB_X21_Y12_N26; Fanout = 2; COMB Node = 'Add0~411'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~409 Add0~411 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.502 ns Add0~413 16 COMB LCCOMB_X21_Y12_N28 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 2.502 ns; Loc. = LCCOMB_X21_Y12_N28; Fanout = 2; COMB Node = 'Add0~413'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~411 Add0~413 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 2.648 ns Add0~415 17 COMB LCCOMB_X21_Y12_N30 2 " "Info: 17: + IC(0.000 ns) + CELL(0.146 ns) = 2.648 ns; Loc. = LCCOMB_X21_Y12_N30; Fanout = 2; COMB Node = 'Add0~415'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.146 ns" { Add0~413 Add0~415 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.719 ns Add0~417 18 COMB LCCOMB_X21_Y11_N0 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.719 ns; Loc. = LCCOMB_X21_Y11_N0; Fanout = 2; COMB Node = 'Add0~417'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~415 Add0~417 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.790 ns Add0~419 19 COMB LCCOMB_X21_Y11_N2 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.790 ns; Loc. = LCCOMB_X21_Y11_N2; Fanout = 2; COMB Node = 'Add0~419'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~417 Add0~419 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.861 ns Add0~421 20 COMB LCCOMB_X21_Y11_N4 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.861 ns; Loc. = LCCOMB_X21_Y11_N4; Fanout = 2; COMB Node = 'Add0~421'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~419 Add0~421 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.932 ns Add0~423 21 COMB LCCOMB_X21_Y11_N6 2 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 2.932 ns; Loc. = LCCOMB_X21_Y11_N6; Fanout = 2; COMB Node = 'Add0~423'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~421 Add0~423 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.003 ns Add0~425 22 COMB LCCOMB_X21_Y11_N8 2 " "Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 3.003 ns; Loc. = LCCOMB_X21_Y11_N8; Fanout = 2; COMB Node = 'Add0~425'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~423 Add0~425 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.074 ns Add0~427 23 COMB LCCOMB_X21_Y11_N10 2 " "Info: 23: + IC(0.000 ns) + CELL(0.071 ns) = 3.074 ns; Loc. = LCCOMB_X21_Y11_N10; Fanout = 2; COMB Node = 'Add0~427'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~425 Add0~427 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.145 ns Add0~429 24 COMB LCCOMB_X21_Y11_N12 2 " "Info: 24: + IC(0.000 ns) + CELL(0.071 ns) = 3.145 ns; Loc. = LCCOMB_X21_Y11_N12; Fanout = 2; COMB Node = 'Add0~429'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~427 Add0~429 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 3.304 ns Add0~431 25 COMB LCCOMB_X21_Y11_N14 2 " "Info: 25: + IC(0.000 ns) + CELL(0.159 ns) = 3.304 ns; Loc. = LCCOMB_X21_Y11_N14; Fanout = 2; COMB Node = 'Add0~431'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~429 Add0~431 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.375 ns Add0~433 26 COMB LCCOMB_X21_Y11_N16 2 " "Info: 26: + IC(0.000 ns) + CELL(0.071 ns) = 3.375 ns; Loc. = LCCOMB_X21_Y11_N16; Fanout = 2; COMB Node = 'Add0~433'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~431 Add0~433 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.446 ns Add0~435 27 COMB LCCOMB_X21_Y11_N18 2 " "Info: 27: + IC(0.000 ns) + CELL(0.071 ns) = 3.446 ns; Loc. = LCCOMB_X21_Y11_N18; Fanout = 2; COMB Node = 'Add0~435'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~433 Add0~435 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.517 ns Add0~437 28 COMB LCCOMB_X21_Y11_N20 2 " "Info: 28: + IC(0.000 ns) + CELL(0.071 ns) = 3.517 ns; Loc. = LCCOMB_X21_Y11_N20; Fanout = 2; COMB Node = 'Add0~437'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~435 Add0~437 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.588 ns Add0~439 29 COMB LCCOMB_X21_Y11_N22 2 " "Info: 29: + IC(0.000 ns) + CELL(0.071 ns) = 3.588 ns; Loc. = LCCOMB_X21_Y11_N22; Fanout = 2; COMB Node = 'Add0~439'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~437 Add0~439 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.659 ns Add0~441 30 COMB LCCOMB_X21_Y11_N24 2 " "Info: 30: + IC(0.000 ns) + CELL(0.071 ns) = 3.659 ns; Loc. = LCCOMB_X21_Y11_N24; Fanout = 2; COMB Node = 'Add0~441'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~439 Add0~441 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.730 ns Add0~443 31 COMB LCCOMB_X21_Y11_N26 2 " "Info: 31: + IC(0.000 ns) + CELL(0.071 ns) = 3.730 ns; Loc. = LCCOMB_X21_Y11_N26; Fanout = 2; COMB Node = 'Add0~443'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~441 Add0~443 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.801 ns Add0~445 32 COMB LCCOMB_X21_Y11_N28 1 " "Info: 32: + IC(0.000 ns) + CELL(0.071 ns) = 3.801 ns; Loc. = LCCOMB_X21_Y11_N28; Fanout = 1; COMB Node = 'Add0~445'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~443 Add0~445 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 4.211 ns Add0~446 33 COMB LCCOMB_X21_Y11_N30 1 " "Info: 33: + IC(0.000 ns) + CELL(0.410 ns) = 4.211 ns; Loc. = LCCOMB_X21_Y11_N30; Fanout = 1; COMB Node = 'Add0~446'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add0~445 Add0~446 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.295 ns cnt1\[31\] 34 REG LCFF_X21_Y11_N31 2 " "Info: 34: + IC(0.000 ns) + CELL(0.084 ns) = 4.295 ns; Loc. = LCFF_X21_Y11_N31; Fanout = 2; REG Node = 'cnt1\[31\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Add0~446 cnt1[31] } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.268 ns ( 76.09 % ) " "Info: Total cell delay = 3.268 ns ( 76.09 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.027 ns ( 23.91 % ) " "Info: Total interconnect delay = 1.027 ns ( 23.91 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.295 ns" { cnt1[0] Add0~385 Add0~387 Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~446 cnt1[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.295 ns" { cnt1[0] Add0~385 Add0~387 Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~446 cnt1[31] } { 0.000ns 1.027ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.373 ns" { clk clk~clkctrl cnt1[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.373 ns" { clk clk~combout clk~clkctrl cnt1[31] } { 0.000ns 0.000ns 0.122ns 0.725ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.372 ns" { clk clk~clkctrl cnt1[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.372 ns" { clk clk~combout clk~clkctrl cnt1[0] } { 0.000ns 0.000ns 0.122ns 0.724ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.295 ns" { cnt1[0] Add0~385 Add0~387 Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~446 cnt1[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.295 ns" { cnt1[0] Add0~385 Add0~387 Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~446 cnt1[31] } { 0.000ns 1.027ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
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