any_div.fit.rpt

在quartus开发环境下

Fitter report for any_div
Fri Mar 30 14:48:42 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Netlist Optimizations
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Delay Chain Summary
 14. Pad To Core Delay Chain Fanout
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Interconnect Usage Summary
 19. LAB Logic Elements
 20. LAB-wide Signals
 21. LAB Signals Sourced
 22. LAB Signals Sourced Out
 23. LAB Distinct Inputs
 24. Fitter Device Options
 25. Fitter Messages
 26. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Fitter Summary                                                                     ;
+------------------------------------+-----------------------------------------------+
; Fitter Status                      ; Successful - Fri Mar 30 14:48:42 2007         ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name                      ; any_div                                       ;
; Top-level Entity Name              ; any_div                                       ;
; Family                             ; Cyclone II                                    ;
; Device                             ; EP2C5T144C6                                   ;
; Timing Models                      ; Final                                         ;
; Total logic elements               ; 45 / 4,608 ( < 1 % )                          ;
; Total registers                    ; 33                                            ;
; Total pins                         ; 2 / 89 ( 2 % )                                ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 0 / 119,808 ( 0 % )                           ;
; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % )                                ;
; Total PLLs                         ; 0 / 2 ( 0 % )                                 ;
+------------------------------------+-----------------------------------------------+


+------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                  ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Option                                         ; Setting                        ; Default Value                  ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Device                                         ; EP2C5T144C6                    ;                                ;
; Use smart compilation                          ; Off                            ; Off                            ;
; Router Timing Optimization Level               ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                    ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                       ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                           ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                    ; Off                            ; Off                            ;
; PowerPlay Power Optimization                   ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing     ; On                             ; On                             ;
; Limit to One Fitting Attempt                   ; Off                            ; Off                            ;
; Final Placement Optimizations                  ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations    ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                  ; 1                              ; 1                              ;
; PCI I/O                                        ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                          ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                      ; Off                            ; Off                            ;
; Auto Global Memory Control Signals             ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II ; Auto                           ; Auto                           ;
; Auto Delay Chains                              ; On                             ; On                             ;
; Auto Merge PLLs                                ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs              ; Off                            ; Off                            ;
; Fitter Effort                                  ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                ; Normal                         ; Normal                         ;
; Auto Global Clock                              ; On                             ; On                             ;
; Auto Global Register Control Signals           ; On                             ; On                             ;
; Always Enable Input Buffers                    ; Off                            ; Off                            ;
+------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                             ;
+---------+-----------------+------------------+---------------------+-----------+----------------------+------------------+
; Node    ; Action          ; Operation        ; Reason              ; Node Port ; Destination Node     ; Destination Port ;
+---------+-----------------+------------------+---------------------+-----------+----------------------+------------------+
; clkdiv1 ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; clkdiv               ; DATAIN           ;
; clkdiv1 ; Duplicated      ; Register Packing ; Timing optimization ; REGOUT    ; clkdiv1~_Duplicate_1 ; REGOUT           ;
+---------+-----------------+------------------+---------------------+-----------+----------------------+------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/my_eda/any_div/any_div.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 45 / 4,608 ( < 1 % ) ;
;     -- Combinational with no register       ; 12                   ;
;     -- Register only                        ; 1                    ;
;     -- Combinational with a register        ; 32                   ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 10                   ;