rs.fit.qmsg

在quartus开发环境下

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 20:51:39 2007 " "Info: Processing started: Thu May 31 20:51:39 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RS -c RS " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off RS -c RS" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "RS EP2C8T144C8 " "Info: Selected device EP2C8T144C8 for design \"RS\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144C8 " "Info: Device EP2C5T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144I8 " "Info: Device EP2C5T144I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144I8 " "Info: Device EP2C8T144I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 76 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 76" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 4 " "Warning: No exact pin location assignment(s) for 4 pins of 4 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "q " "Info: Pin q not assigned to an exact location on the device" {  } { { "RS.vhd" "" { Text "D:/my_eda/RS/RS.vhd" 6 -1 0 } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { q } "NODE_NAME" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { q } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "qn " "Info: Pin qn not assigned to an exact location on the device" {  } { { "RS.vhd" "" { Text "D:/my_eda/RS/RS.vhd" 6 -1 0 } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { qn } "NODE_NAME" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { qn } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "r " "Info: Pin r not assigned to an exact location on the device" {  } { { "RS.vhd" "" { Text "D:/my_eda/RS/RS.vhd" 5 -1 0 } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { r } "NODE_NAME" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { r } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "s " "Info: Pin s not assigned to an exact location on the device" {  } { { "RS.vhd" "" { Text "D:/my_eda/RS/RS.vhd" 5 -1 0 } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { s } "NODE_NAME" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { s } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "4 unused 3.30 2 2 0 " "Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 2 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 15 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  15 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 23 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 20 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 24 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0}  } {  } 0 0 "Statistics of %1!s!" 0 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X10_Y9 " "Info: The peak interconnect region extends from location X0_Y0 to location X10_Y9" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "2 " "Warning: Found 2 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "q 0 " "Info: Pin \"q\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "qn 0 " "Info: Pin \"qn\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "175 " "Info: Allocated 175 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 20:51:52 2007 " "Info: Processing ended: Thu May 31 20:51:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/my_eda/RS/RS.fit.smsg " "Info: Generated suppressed messages file D:/my_eda/RS/RS.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}