📄 rs.fit.smsg
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Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Thu May 31 20:51:39 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off RS -c RS
Info: Selected device EP2C8T144C8 for design "RS"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP2C5T144C8 is compatible
Info: Device EP2C5T144I8 is compatible
Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 4 pins of 4 total pins
Info: Pin q not assigned to an exact location on the device
Info: Pin qn not assigned to an exact location on the device
Info: Pin r not assigned to an exact location on the device
Info: Pin s not assigned to an exact location on the device
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 2 input, 2 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used -- 15 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 23 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 20 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
Info: The peak interconnect region extends from location X0_Y0 to location X10_Y9
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 2 output pins without output pin load capacitance assignment
Info: Pin "q" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "qn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
Info: Allocated 175 megabytes of memory during processing
Info: Processing ended: Thu May 31 20:51:52 2007
Info: Elapsed time: 00:00:13
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