rs.vhd

来自「在quartus开发环境下」· VHDL 代码 · 共 15 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RS is
port(s,r:in std_logic;
     q,qn:out std_logic);
end;
architecture one of RS is
signal q1,qn1:std_logic;
begin 
q1<=s nand qn1;
qn1<=r nand q1;
q<=q1;
qn<=qn1;
end;