yxbianma8_3.map.qmsg

在quartus开发环境下

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 16:12:25 2007 " "Info: Processing started: Thu May 31 16:12:25 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off yxbianma8_3 -c yxbianma8_3 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off yxbianma8_3 -c yxbianma8_3" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yxbianma8_3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file yxbianma8_3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 yxbianma8_3-one " "Info: Found design unit 1: yxbianma8_3-one" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 yxbianma8_3 " "Info: Found entity 1: yxbianma8_3" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "yxbianma8_3 " "Info: Elaborating entity \"yxbianma8_3\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y yxbianma8_3.vhd(11) " "Warning (10631): VHDL Process Statement warning at yxbianma8_3.vhd(11): inferring latch(es) for signal or variable \"y\", which holds its previous value in one or more paths through the process" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "gs yxbianma8_3.vhd(11) " "Warning (10631): VHDL Process Statement warning at yxbianma8_3.vhd(11): inferring latch(es) for signal or variable \"gs\", which holds its previous value in one or more paths through the process" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "eo yxbianma8_3.vhd(11) " "Warning (10631): VHDL Process Statement warning at yxbianma8_3.vhd(11): inferring latch(es) for signal or variable \"eo\", which holds its previous value in one or more paths through the process" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "eo yxbianma8_3.vhd(11) " "Info (10041): Verilog HDL or VHDL info at yxbianma8_3.vhd(11): inferred latch for \"eo\"" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "gs yxbianma8_3.vhd(11) " "Info (10041): Verilog HDL or VHDL info at yxbianma8_3.vhd(11): inferred latch for \"gs\"" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "y\[0\] yxbianma8_3.vhd(11) " "Info (10041): Verilog HDL or VHDL info at yxbianma8_3.vhd(11): inferred latch for \"y\[0\]\"" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "y\[1\] yxbianma8_3.vhd(11) " "Info (10041): Verilog HDL or VHDL info at yxbianma8_3.vhd(11): inferred latch for \"y\[1\]\"" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "y\[2\] yxbianma8_3.vhd(11) " "Info (10041): Verilog HDL or VHDL info at yxbianma8_3.vhd(11): inferred latch for \"y\[2\]\"" {  } { { "yxbianma8_3.vhd" "" { Text "D:/my_eda/yxbianma8_3/yxbianma8_3.vhd" 11 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "24 " "Info: Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "10 " "Info: Implemented 10 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 16:12:30 2007 " "Info: Processing ended: Thu May 31 16:12:30 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}