add4.vhd

来自「在quartus开发环境下」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add4 is
port(a:in std_logic_vector(3 downto 0);
     b:in std_logic_vector(3 downto 0);
     ci:in std_logic;
     s:out std_logic_vector(3 downto 0);
     co:out std_logic);
end;
architecture one of add4 is
signal temp:std_logic_vector(4 downto 0);
begin
temp<=('0'&a)+b+ci;
s<=temp(3 downto 0);
co<=temp(4);
end;