any_div_1.vhd

在quartus开发环境下

--任意整数分频的VHDL代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity any_div_1 IS
generic(n:integer:=6);
port(
	clk: IN STD_LOGIC;
	clkout_3:BUFFER STD_LOGIC);
end ;
architecture A OF any_div_1 IS
	SIGNAL cnt1,cnt2:integer:=0;
	SIGNAL outtemp:STD_LOGIC;
	SIGNAL LOUT:STD_LOGIC;
	SIGNAL OUT3:STD_LOGIC:='0';
begin

process(clk)
begin
IF clk'EVENT AND clk='1'THEN
	IF cnt1=n-1 THEN
	cnt1<=0;
	else
	cnt1<=cnt1+1;
	end IF;
end IF;
end process;

process(clk)
begin
IF clk'EVENT AND clk='0'THEN
	IF cnt2=n-1 THEN
	cnt2<=0;
	else 
	cnt2<=cnt2+1;
	end IF;
end IF;
end process;

process(cnt1,cnt2 )
begin
if ((n mod 2)=1) then
	IF cnt1=1 THEN
		IF cnt2=0 THEN
		outtemp<='1';
		else outtemp<='0';
		end IF;

	ELSIF cnt1=(n+1)/2 THEN
		IF cnt2=(n+1)/2 THEN
		outtemp<='1';
		else outtemp<='0';
		end IF;

	else 
	outtemp<='0';
	end IF;
else
if cnt1=1 then
	outtemp<='1';
	elsif (cnt1=(n/2+1)) then
	outtemp<='1';
	else
	outtemp<='0';
	end if;
end if;
end process;

process(outtemp,clk)
begin
if ((n/=2) and (n/=1)) then
	IF outtemp'EVENT AND outtemp='1' THEN
	clkout_3<=NOT clkout_3;
	end IF;
elsif (n=2) then
	if(clk'event and clk='1')then
	clkout_3<=not clkout_3;
	end if;
else
clkout_3<=clk;
end if;
end process;
end A;

--只要把n设置成你要分频的数值就可以了