any_div_1.tan.qmsg

在quartus开发环境下

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "clkout_3~reg0 clkout_3~reg0 clk 1.911 ns " "Info: Found hold time violation between source  pin or register \"clkout_3~reg0\" and destination pin or register \"clkout_3~reg0\" for clock \"clk\" (Hold time is 1.911 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.302 ns + Largest " "Info: + Largest clock skew is 2.302 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.432 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.432 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.787 ns) 2.599 ns cnt1\[12\] 3 REG LCFF_X27_Y6_N25 3 " "Info: 3: + IC(0.701 ns) + CELL(0.787 ns) = 2.599 ns; Loc. = LCFF_X27_Y6_N25; Fanout = 3; REG Node = 'cnt1\[12\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.488 ns" { clk~clkctrl cnt1[12] } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.398 ns) 4.044 ns Equal0~340 4 COMB LCCOMB_X26_Y5_N24 1 " "Info: 4: + IC(1.047 ns) + CELL(0.398 ns) = 4.044 ns; Loc. = LCCOMB_X26_Y5_N24; Fanout = 1; COMB Node = 'Equal0~340'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.445 ns" { cnt1[12] Equal0~340 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.410 ns) 4.721 ns Equal0~342 5 COMB LCCOMB_X26_Y5_N16 1 " "Info: 5: + IC(0.267 ns) + CELL(0.410 ns) = 4.721 ns; Loc. = LCCOMB_X26_Y5_N16; Fanout = 1; COMB Node = 'Equal0~342'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.677 ns" { Equal0~340 Equal0~342 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.258 ns) + CELL(0.275 ns) 5.254 ns Equal0~347 6 COMB LCCOMB_X26_Y5_N10 3 " "Info: 6: + IC(0.258 ns) + CELL(0.275 ns) = 5.254 ns; Loc. = LCCOMB_X26_Y5_N10; Fanout = 3; COMB Node = 'Equal0~347'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.533 ns" { Equal0~342 Equal0~347 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.150 ns) 5.663 ns outtemp~39 7 COMB LCCOMB_X26_Y5_N20 1 " "Info: 7: + IC(0.259 ns) + CELL(0.150 ns) = 5.663 ns; Loc. = LCCOMB_X26_Y5_N20; Fanout = 1; COMB Node = 'outtemp~39'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.409 ns" { Equal0~347 outtemp~39 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.537 ns) 6.432 ns clkout_3~reg0 8 REG LCFF_X26_Y5_N19 2 " "Info: 8: + IC(0.232 ns) + CELL(0.537 ns) = 6.432 ns; Loc. = LCFF_X26_Y5_N19; Fanout = 2; REG Node = 'clkout_3~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.769 ns" { outtemp~39 clkout_3~reg0 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.546 ns ( 55.13 % ) " "Info: Total cell delay = 3.546 ns ( 55.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.886 ns ( 44.87 % ) " "Info: Total interconnect delay = 2.886 ns ( 44.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "6.432 ns" { clk clk~clkctrl cnt1[12] Equal0~340 Equal0~342 Equal0~347 outtemp~39 clkout_3~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "6.432 ns" { clk clk~combout clk~clkctrl cnt1[12] Equal0~340 Equal0~342 Equal0~347 outtemp~39 clkout_3~reg0 } { 0.000ns 0.000ns 0.122ns 0.701ns 1.047ns 0.267ns 0.258ns 0.259ns 0.232ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.398ns 0.410ns 0.275ns 0.150ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.130 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 4.130 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.787 ns) 2.611 ns cnt1\[2\] 3 REG LCFF_X26_Y5_N13 5 " "Info: 3: + IC(0.713 ns) + CELL(0.787 ns) = 2.611 ns; Loc. = LCFF_X26_Y5_N13; Fanout = 5; REG Node = 'cnt1\[2\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { clk~clkctrl cnt1[2] } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.342 ns) + CELL(0.408 ns) 3.361 ns outtemp~39 4 COMB LCCOMB_X26_Y5_N20 1 " "Info: 4: + IC(0.342 ns) + CELL(0.408 ns) = 3.361 ns; Loc. = LCCOMB_X26_Y5_N20; Fanout = 1; COMB Node = 'outtemp~39'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.750 ns" { cnt1[2] outtemp~39 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.537 ns) 4.130 ns clkout_3~reg0 5 REG LCFF_X26_Y5_N19 2 " "Info: 5: + IC(0.232 ns) + CELL(0.537 ns) = 4.130 ns; Loc. = LCFF_X26_Y5_N19; Fanout = 2; REG Node = 'clkout_3~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.769 ns" { outtemp~39 clkout_3~reg0 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.721 ns ( 65.88 % ) " "Info: Total cell delay = 2.721 ns ( 65.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.409 ns ( 34.12 % ) " "Info: Total interconnect delay = 1.409 ns ( 34.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.130 ns" { clk clk~clkctrl cnt1[2] outtemp~39 clkout_3~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.130 ns" { clk clk~combout clk~clkctrl cnt1[2] outtemp~39 clkout_3~reg0 } { 0.000ns 0.000ns 0.122ns 0.713ns 0.342ns 0.232ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.408ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "6.432 ns" { clk clk~clkctrl cnt1[12] Equal0~340 Equal0~342 Equal0~347 outtemp~39 clkout_3~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "6.432 ns" { clk clk~combout clk~clkctrl cnt1[12] Equal0~340 Equal0~342 Equal0~347 outtemp~39 clkout_3~reg0 } { 0.000ns 0.000ns 0.122ns 0.701ns 1.047ns 0.267ns 0.258ns 0.259ns 0.232ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.398ns 0.410ns 0.275ns 0.150ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.130 ns" { clk clk~clkctrl cnt1[2] outtemp~39 clkout_3~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.130 ns" { clk clk~combout clk~clkctrl cnt1[2] outtemp~39 clkout_3~reg0 } { 0.000ns 0.000ns 0.122ns 0.713ns 0.342ns 0.232ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.408ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 73 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns - Shortest register register " "Info: - Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkout_3~reg0 1 REG LCFF_X26_Y5_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y5_N19; Fanout = 2; REG Node = 'clkout_3~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkout_3~reg0 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns clkout_3~3 2 COMB LCCOMB_X26_Y5_N18 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X26_Y5_N18; Fanout = 1; COMB Node = 'clkout_3~3'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { clkout_3~reg0 clkout_3~3 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns clkout_3~reg0 3 REG LCFF_X26_Y5_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X26_Y5_N19; Fanout = 2; REG Node = 'clkout_3~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { clkout_3~3 clkout_3~reg0 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { clkout_3~reg0 clkout_3~3 clkout_3~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { clkout_3~reg0 clkout_3~3 clkout_3~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 73 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "6.432 ns" { clk clk~clkctrl cnt1[12] Equal0~340 Equal0~342 Equal0~347 outtemp~39 clkout_3~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "6.432 ns" { clk clk~combout clk~clkctrl cnt1[12] Equal0~340 Equal0~342 Equal0~347 outtemp~39 clkout_3~reg0 } { 0.000ns 0.000ns 0.122ns 0.701ns 1.047ns 0.267ns 0.258ns 0.259ns 0.232ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.398ns 0.410ns 0.275ns 0.150ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.130 ns" { clk clk~clkctrl cnt1[2] outtemp~39 clkout_3~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.130 ns" { clk clk~combout clk~clkctrl cnt1[2] outtemp~39 clkout_3~reg0 } { 0.000ns 0.000ns 0.122ns 0.713ns 0.342ns 0.232ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.408ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { clkout_3~reg0 clkout_3~3 clkout_3~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { clkout_3~reg0 clkout_3~3 clkout_3~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}