any_div_1.tan.qmsg

在quartus开发环境下

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "41 " "Warning: Found 41 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cnt1\[10\] " "Info: Detected ripple clock \"cnt1\[10\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[7\] " "Info: Detected ripple clock \"cnt1\[7\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[8\] " "Info: Detected ripple clock \"cnt1\[8\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[9\] " "Info: Detected ripple clock \"cnt1\[9\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[15\] " "Info: Detected ripple clock \"cnt1\[15\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[18\] " "Info: Detected ripple clock \"cnt1\[18\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[18\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[16\] " "Info: Detected ripple clock \"cnt1\[16\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[16\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[17\] " "Info: Detected ripple clock \"cnt1\[17\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[17\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[22\] " "Info: Detected ripple clock \"cnt1\[22\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[22\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[21\] " "Info: Detected ripple clock \"cnt1\[21\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[21\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[20\] " "Info: Detected ripple clock \"cnt1\[20\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[20\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[19\] " "Info: Detected ripple clock \"cnt1\[19\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[19\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[11\] " "Info: Detected ripple clock \"cnt1\[11\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[13\] " "Info: Detected ripple clock \"cnt1\[13\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[14\] " "Info: Detected ripple clock \"cnt1\[14\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[14\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[12\] " "Info: Detected ripple clock \"cnt1\[12\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[28\] " "Info: Detected ripple clock \"cnt1\[28\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[28\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[27\] " "Info: Detected ripple clock \"cnt1\[27\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[27\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[26\] " "Info: Detected ripple clock \"cnt1\[26\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[26\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[29\] " "Info: Detected ripple clock \"cnt1\[29\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[29\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[25\] " "Info: Detected ripple clock \"cnt1\[25\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[25\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[24\] " "Info: Detected ripple clock \"cnt1\[24\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[23\] " "Info: Detected ripple clock \"cnt1\[23\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[23\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[1\] " "Info: Detected ripple clock \"cnt1\[1\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~341 " "Info: Detected gated clock \"Equal0~341\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~341" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~339 " "Info: Detected gated clock \"Equal0~339\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~339" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~338 " "Info: Detected gated clock \"Equal0~338\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~338" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~340 " "Info: Detected gated clock \"Equal0~340\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~340" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[30\] " "Info: Detected ripple clock \"cnt1\[30\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[30\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~345 " "Info: Detected gated clock \"Equal0~345\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~345" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[31\] " "Info: Detected ripple clock \"cnt1\[31\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[31\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[5\] " "Info: Detected ripple clock \"cnt1\[5\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[6\] " "Info: Detected ripple clock \"cnt1\[6\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[4\] " "Info: Detected ripple clock \"cnt1\[4\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[3\] " "Info: Detected ripple clock \"cnt1\[3\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~344 " "Info: Detected gated clock \"Equal0~344\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~344" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~346 " "Info: Detected gated clock \"Equal0~346\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~346" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~343 " "Info: Detected gated clock \"Equal0~343\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 22 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~343" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[0\] " "Info: Detected ripple clock \"cnt1\[0\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[2\] " "Info: Detected ripple clock \"cnt1\[2\]\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "outtemp~39 " "Info: Detected gated clock \"outtemp~39\" as buffer" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 14 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "outtemp~39" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt1\[2\] register cnt1\[31\] 242.78 MHz 4.119 ns Internal " "Info: Clock \"clk\" has Internal fmax of 242.78 MHz between source register \"cnt1\[2\]\" and destination register \"cnt1\[31\]\" (period= 4.119 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.905 ns + Longest register register " "Info: + Longest register to register delay is 3.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt1\[2\] 1 REG LCFF_X26_Y5_N13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y5_N13; Fanout = 5; REG Node = 'cnt1\[2\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt1[2] } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.393 ns) 1.172 ns Add0~389 2 COMB LCCOMB_X27_Y6_N4 2 " "Info: 2: + IC(0.779 ns) + CELL(0.393 ns) = 1.172 ns; Loc. = LCCOMB_X27_Y6_N4; Fanout = 2; COMB Node = 'Add0~389'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.172 ns" { cnt1[2] Add0~389 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.243 ns Add0~391 3 COMB LCCOMB_X27_Y6_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.243 ns; Loc. = LCCOMB_X27_Y6_N6; Fanout = 2; COMB Node = 'Add0~391'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~389 Add0~391 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.314 ns Add0~393 4 COMB LCCOMB_X27_Y6_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.314 ns; Loc. = LCCOMB_X27_Y6_N8; Fanout = 2; COMB Node = 'Add0~393'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~391 Add0~393 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.385 ns Add0~395 5 COMB LCCOMB_X27_Y6_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.385 ns; Loc. = LCCOMB_X27_Y6_N10; Fanout = 2; COMB Node = 'Add0~395'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~393 Add0~395 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.456 ns Add0~397 6 COMB LCCOMB_X27_Y6_N12 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.456 ns; Loc. = LCCOMB_X27_Y6_N12; Fanout = 2; COMB Node = 'Add0~397'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~395 Add0~397 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.615 ns Add0~399 7 COMB LCCOMB_X27_Y6_N14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.159 ns) = 1.615 ns; Loc. = LCCOMB_X27_Y6_N14; Fanout = 2; COMB Node = 'Add0~399'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~397 Add0~399 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.686 ns Add0~401 8 COMB LCCOMB_X27_Y6_N16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.686 ns; Loc. = LCCOMB_X27_Y6_N16; Fanout = 2; COMB Node = 'Add0~401'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~399 Add0~401 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.757 ns Add0~403 9 COMB LCCOMB_X27_Y6_N18 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.757 ns; Loc. = LCCOMB_X27_Y6_N18; Fanout = 2; COMB Node = 'Add0~403'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~401 Add0~403 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.828 ns Add0~405 10 COMB LCCOMB_X27_Y6_N20 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.828 ns; Loc. = LCCOMB_X27_Y6_N20; Fanout = 2; COMB Node = 'Add0~405'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~403 Add0~405 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.899 ns Add0~407 11 COMB LCCOMB_X27_Y6_N22 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.899 ns; Loc. = LCCOMB_X27_Y6_N22; Fanout = 2; COMB Node = 'Add0~407'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~405 Add0~407 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.970 ns Add0~409 12 COMB LCCOMB_X27_Y6_N24 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.970 ns; Loc. = LCCOMB_X27_Y6_N24; Fanout = 2; COMB Node = 'Add0~409'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~407 Add0~409 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.041 ns Add0~411 13 COMB LCCOMB_X27_Y6_N26 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 2.041 ns; Loc. = LCCOMB_X27_Y6_N26; Fanout = 2; COMB Node = 'Add0~411'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~409 Add0~411 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.112 ns Add0~413 14 COMB LCCOMB_X27_Y6_N28 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 2.112 ns; Loc. = LCCOMB_X27_Y6_N28; Fanout = 2; COMB Node = 'Add0~413'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~411 Add0~413 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 2.258 ns Add0~415 15 COMB LCCOMB_X27_Y6_N30 2 " "Info: 15: + IC(0.000 ns) + CELL(0.146 ns) = 2.258 ns; Loc. = LCCOMB_X27_Y6_N30; Fanout = 2; COMB Node = 'Add0~415'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.146 ns" { Add0~413 Add0~415 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.329 ns Add0~417 16 COMB LCCOMB_X27_Y5_N0 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 2.329 ns; Loc. = LCCOMB_X27_Y5_N0; Fanout = 2; COMB Node = 'Add0~417'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~415 Add0~417 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.400 ns Add0~419 17 COMB LCCOMB_X27_Y5_N2 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 2.400 ns; Loc. = LCCOMB_X27_Y5_N2; Fanout = 2; COMB Node = 'Add0~419'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~417 Add0~419 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.471 ns Add0~421 18 COMB LCCOMB_X27_Y5_N4 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.471 ns; Loc. = LCCOMB_X27_Y5_N4; Fanout = 2; COMB Node = 'Add0~421'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~419 Add0~421 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.542 ns Add0~423 19 COMB LCCOMB_X27_Y5_N6 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.542 ns; Loc. = LCCOMB_X27_Y5_N6; Fanout = 2; COMB Node = 'Add0~423'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~421 Add0~423 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.613 ns Add0~425 20 COMB LCCOMB_X27_Y5_N8 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.613 ns; Loc. = LCCOMB_X27_Y5_N8; Fanout = 2; COMB Node = 'Add0~425'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~423 Add0~425 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.684 ns Add0~427 21 COMB LCCOMB_X27_Y5_N10 2 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 2.684 ns; Loc. = LCCOMB_X27_Y5_N10; Fanout = 2; COMB Node = 'Add0~427'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~425 Add0~427 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.755 ns Add0~429 22 COMB LCCOMB_X27_Y5_N12 2 " "Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 2.755 ns; Loc. = LCCOMB_X27_Y5_N12; Fanout = 2; COMB Node = 'Add0~429'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~427 Add0~429 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.914 ns Add0~431 23 COMB LCCOMB_X27_Y5_N14 2 " "Info: 23: + IC(0.000 ns) + CELL(0.159 ns) = 2.914 ns; Loc. = LCCOMB_X27_Y5_N14; Fanout = 2; COMB Node = 'Add0~431'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { Add0~429 Add0~431 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.985 ns Add0~433 24 COMB LCCOMB_X27_Y5_N16 2 " "Info: 24: + IC(0.000 ns) + CELL(0.071 ns) = 2.985 ns; Loc. = LCCOMB_X27_Y5_N16; Fanout = 2; COMB Node = 'Add0~433'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~431 Add0~433 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.056 ns Add0~435 25 COMB LCCOMB_X27_Y5_N18 2 " "Info: 25: + IC(0.000 ns) + CELL(0.071 ns) = 3.056 ns; Loc. = LCCOMB_X27_Y5_N18; Fanout = 2; COMB Node = 'Add0~435'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~433 Add0~435 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.127 ns Add0~437 26 COMB LCCOMB_X27_Y5_N20 2 " "Info: 26: + IC(0.000 ns) + CELL(0.071 ns) = 3.127 ns; Loc. = LCCOMB_X27_Y5_N20; Fanout = 2; COMB Node = 'Add0~437'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~435 Add0~437 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.198 ns Add0~439 27 COMB LCCOMB_X27_Y5_N22 2 " "Info: 27: + IC(0.000 ns) + CELL(0.071 ns) = 3.198 ns; Loc. = LCCOMB_X27_Y5_N22; Fanout = 2; COMB Node = 'Add0~439'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~437 Add0~439 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.269 ns Add0~441 28 COMB LCCOMB_X27_Y5_N24 2 " "Info: 28: + IC(0.000 ns) + CELL(0.071 ns) = 3.269 ns; Loc. = LCCOMB_X27_Y5_N24; Fanout = 2; COMB Node = 'Add0~441'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~439 Add0~441 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.340 ns Add0~443 29 COMB LCCOMB_X27_Y5_N26 2 " "Info: 29: + IC(0.000 ns) + CELL(0.071 ns) = 3.340 ns; Loc. = LCCOMB_X27_Y5_N26; Fanout = 2; COMB Node = 'Add0~443'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~441 Add0~443 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.411 ns Add0~445 30 COMB LCCOMB_X27_Y5_N28 1 " "Info: 30: + IC(0.000 ns) + CELL(0.071 ns) = 3.411 ns; Loc. = LCCOMB_X27_Y5_N28; Fanout = 1; COMB Node = 'Add0~445'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { Add0~443 Add0~445 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.821 ns Add0~446 31 COMB LCCOMB_X27_Y5_N30 1 " "Info: 31: + IC(0.000 ns) + CELL(0.410 ns) = 3.821 ns; Loc. = LCCOMB_X27_Y5_N30; Fanout = 1; COMB Node = 'Add0~446'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { Add0~445 Add0~446 } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.905 ns cnt1\[31\] 32 REG LCFF_X27_Y5_N31 2 " "Info: 32: + IC(0.000 ns) + CELL(0.084 ns) = 3.905 ns; Loc. = LCFF_X27_Y5_N31; Fanout = 2; REG Node = 'cnt1\[31\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Add0~446 cnt1[31] } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns ( 80.05 % ) " "Info: Total cell delay = 3.126 ns ( 80.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.779 ns ( 19.95 % ) " "Info: Total interconnect delay = 0.779 ns ( 19.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.905 ns" { cnt1[2] Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~446 cnt1[31] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.905 ns" { cnt1[2] Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~446 cnt1[31] } { 0.000ns 0.779ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.361 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.537 ns) 2.361 ns cnt1\[31\] 3 REG LCFF_X27_Y5_N31 2 " "Info: 3: + IC(0.713 ns) + CELL(0.537 ns) = 2.361 ns; Loc. = LCFF_X27_Y5_N31; Fanout = 2; REG Node = 'cnt1\[31\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.250 ns" { clk~clkctrl cnt1[31] } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.63 % ) " "Info: Total cell delay = 1.526 ns ( 64.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.835 ns ( 35.37 % ) " "Info: Total interconnect delay = 0.835 ns ( 35.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.361 ns" { clk clk~clkctrl cnt1[31] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.361 ns" { clk clk~combout clk~clkctrl cnt1[31] } { 0.000ns 0.000ns 0.122ns 0.713ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.361 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.537 ns) 2.361 ns cnt1\[2\] 3 REG LCFF_X26_Y5_N13 5 " "Info: 3: + IC(0.713 ns) + CELL(0.537 ns) = 2.361 ns; Loc. = LCFF_X26_Y5_N13; Fanout = 5; REG Node = 'cnt1\[2\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.250 ns" { clk~clkctrl cnt1[2] } "NODE_NAME" } } { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.63 % ) " "Info: Total cell delay = 1.526 ns ( 64.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.835 ns ( 35.37 % ) " "Info: Total interconnect delay = 0.835 ns ( 35.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.361 ns" { clk clk~clkctrl cnt1[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.361 ns" { clk clk~combout clk~clkctrl cnt1[2] } { 0.000ns 0.000ns 0.122ns 0.713ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.361 ns" { clk clk~clkctrl cnt1[31] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.361 ns" { clk clk~combout clk~clkctrl cnt1[31] } { 0.000ns 0.000ns 0.122ns 0.713ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.361 ns" { clk clk~clkctrl cnt1[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.361 ns" { clk clk~combout clk~clkctrl cnt1[2] } { 0.000ns 0.000ns 0.122ns 0.713ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "any_div_1.vhd" "" { Text "D:/my_eda/any_div_1/any_div_1.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.905 ns" { cnt1[2] Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~446 cnt1[31] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.905 ns" { cnt1[2] Add0~389 Add0~391 Add0~393 Add0~395 Add0~397 Add0~399 Add0~401 Add0~403 Add0~405 Add0~407 Add0~409 Add0~411 Add0~413 Add0~415 Add0~417 Add0~419 Add0~421 Add0~423 Add0~425 Add0~427 Add0~429 Add0~431 Add0~433 Add0~435 Add0~437 Add0~439 Add0~441 Add0~443 Add0~445 Add0~446 cnt1[31] } { 0.000ns 0.779ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.361 ns" { clk clk~clkctrl cnt1[31] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.361 ns" { clk clk~combout clk~clkctrl cnt1[31] } { 0.000ns 0.000ns 0.122ns 0.713ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.361 ns" { clk clk~clkctrl cnt1[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "2.361 ns" { clk clk~combout clk~clkctrl cnt1[2] } { 0.000ns 0.000ns 0.122ns 0.713ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}