ram.sim.rpt

在quartus开发环境下

; Total output ports checked                          ; 1522         ;
; Total output ports with complete 1/0-value coverage ; 679          ;
; Total output ports with no 1/0-value coverage       ; 438          ;
; Total output ports with no 1-value coverage         ; 711          ;
; Total output ports with no 0-value coverage         ; 570          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                            ;
+------------------------------------------------------------------+------------------------------------------------------------------+------------------+
; Node Name                                                        ; Output Port Name                                                 ; Output Port Type ;
+------------------------------------------------------------------+------------------------------------------------------------------+------------------+
; |ram|process0~0                                                  ; |ram|process0~0                                                  ; out0             ;
; |ram|comb~0                                                      ; |ram|comb~0                                                      ; out              ;
; |ram|comb~2                                                      ; |ram|comb~2                                                      ; out              ;
; |ram|comb~3                                                      ; |ram|comb~3                                                      ; out              ;
; |ram|comb~4                                                      ; |ram|comb~4                                                      ; out              ;
; |ram|comb~5                                                      ; |ram|comb~5                                                      ; out              ;
; |ram|addr[0]                                                     ; |ram|addr[0]                                                     ; out              ;
; |ram|addr[1]                                                     ; |ram|addr[1]                                                     ; out              ;
; |ram|wr                                                          ; |ram|wr                                                          ; out              ;
; |ram|datain[0]                                                   ; |ram|datain[0]                                                   ; out              ;
; |ram|datain[2]                                                   ; |ram|datain[2]                                                   ; out              ;
; |ram|datain[3]                                                   ; |ram|datain[3]                                                   ; out              ;
; |ram|datain[4]                                                   ; |ram|datain[4]                                                   ; out              ;
; |ram|dataout[0]                                                  ; |ram|dataout[0]                                                  ; pin_out          ;
; |ram|dataout[2]                                                  ; |ram|dataout[2]                                                  ; pin_out          ;
; |ram|dataout[3]                                                  ; |ram|dataout[3]                                                  ; pin_out          ;
; |ram|dataout[4]                                                  ; |ram|dataout[4]                                                  ; pin_out          ;
; |ram|dataout[5]                                                  ; |ram|dataout[5]                                                  ; pin_out          ;
; |ram|rtl~1                                                       ; |ram|rtl~1                                                       ; out0             ;
; |ram|rtl~2                                                       ; |ram|rtl~2                                                       ; out0             ;
; |ram|rtl~3                                                       ; |ram|rtl~3                                                       ; out0             ;
; |ram|data1~353                                                   ; |ram|data1~353                                                   ; out0             ;
; |ram|data1~354                                                   ; |ram|data1~354                                                   ; out0             ;
; |ram|data1~355                                                   ; |ram|data1~355                                                   ; out0             ;
; |ram|data1~385                                                   ; |ram|data1~385                                                   ; out              ;
; |ram|data1~386                                                   ; |ram|data1~386                                                   ; out              ;
; |ram|data1~387                                                   ; |ram|data1~387                                                   ; out              ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|result_node[0]~1 ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|result_node[0]~1 ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|result_node[0]   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|result_node[0]   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~2              ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~2              ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result111w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result111w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result111w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result111w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~6              ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~6              ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result112w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result112w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result112w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result112w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~10             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~10             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~11             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~11             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~12             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~12             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result120w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result120w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result120w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result120w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~14             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~14             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~15             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~15             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result121w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result121w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result121w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result121w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~18             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~18             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~19             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~19             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result122w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result122w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result122w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result122w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~22             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~22             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~23             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~23             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result123w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result123w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result123w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result123w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~25             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~25             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~27             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~27             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~28             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~28             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result135w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result135w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result135w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result135w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~29             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~29             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~31             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~31             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result156w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result156w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result156w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result156w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~33             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~33             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~35             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~35             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result173w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result173w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result173w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result173w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~37             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~37             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~39             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~39             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result190w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result190w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result190w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result190w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~42             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~42             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result206w~0   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result206w~0   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~44             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~44             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result206w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result206w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~46             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~46             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~47             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~47             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result223w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result223w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result223w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result223w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~50             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~50             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~51             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~51             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result224w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result224w~1   ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result224w     ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result224w     ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~54             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~54             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~55             ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|_~55             ; out0             ;
; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result225w~1   ; |ram|lpm_mux:data1_rtl_7|mux_klc:auto_generated|w_result225w~1   ; out0             ;