lifo.map.rpt

在quartus开发环境下

; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; lifo.vhd                         ; yes             ; User VHDL File  ; D:/my_eda/LIFO/lifo.vhd      ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 78    ;
;                                             ;       ;
; Total combinational functions               ; 68    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 43    ;
;     -- 3 input functions                    ; 23    ;
;     -- <=2 input functions                  ; 2     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 68    ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 78    ;
;     -- Dedicated logic registers            ; 78    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 22    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 78    ;
; Total fan-out                               ; 520   ;
; Average fan-out                             ; 3.10  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |lifo                      ; 68 (68)           ; 78 (78)      ; 0           ; 0            ; 0       ; 0         ; 22   ; 0            ; |lifo               ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; stack[8][0]                           ; Stuck at GND due to stuck port data_in ;
; stack[8][1]                           ; Stuck at GND due to stuck port data_in ;
; stack[8][2]                           ; Stuck at GND due to stuck port data_in ;
; stack[8][3]                           ; Stuck at GND due to stuck port data_in ;
; stack[8][4]                           ; Stuck at GND due to stuck port data_in ;
; stack[8][5]                           ; Stuck at GND due to stuck port data_in ;
; stack[8][6]                           ; Stuck at GND due to stuck port data_in ;
; stack[8][7]                           ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 8 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 78    ;
; Number of registers using Synchronous Clear  ; 8     ;
; Number of registers using Synchronous Load   ; 8     ;
; Number of registers using Asynchronous Clear ; 13    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 72    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |lifo|cnt[1]               ;
; 11:1               ; 8 bits    ; 56 LEs        ; 48 LEs               ; 8 LEs                  ; Yes        ; |lifo|dout[0]~reg0         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Apr 05 16:56:46 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lifo -c lifo
Info: Found 2 design units, including 1 entities, in source file lifo.vhd
    Info: Found design unit 1: lifo-one
    Info: Found entity 1: lifo
Info: Elaborating entity "lifo" for the top level hierarchy
Warning: Reduced register "stack[8][0]" with stuck data_in port to stuck value GND
Warning: Reduced register "stack[8][1]" with stuck data_in port to stuck value GND
Warning: Reduced register "stack[8][2]" with stuck data_in port to stuck value GND
Warning: Reduced register "stack[8][3]" with stuck data_in port to stuck value GND
Warning: Reduced register "stack[8][4]" with stuck data_in port to stuck value GND
Warning: Reduced register "stack[8][5]" with stuck data_in port to stuck value GND
Warning: Reduced register "stack[8][6]" with stuck data_in port to stuck value GND
Warning: Reduced register "stack[8][7]" with stuck data_in port to stuck value GND
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Allocated 141 megabytes of memory during processing
    Info: Processing ended: Thu Apr 05 16:56:51 2007
    Info: Elapsed time: 00:00:05
Info: *******************************************************************
Info: Running Quartus II Partition Merge
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Apr 05 16:56:52 2007
Info: Implemented 154 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 10 output pins
    Info: Implemented 132 logic cells
Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Apr 05 16:56:53 2007
    Info: Elapsed time: 00:00:01