📄 lifo.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[0\] register dout\[3\]~reg0 168.86 MHz 5.922 ns Internal " "Info: Clock \"clk\" has Internal fmax of 168.86 MHz between source register \"cnt\[0\]\" and destination register \"dout\[3\]~reg0\" (period= 5.922 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.656 ns + Longest register register " "Info: + Longest register to register delay is 5.656 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LCFF_X19_Y9_N19 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y9_N19; Fanout = 26; REG Node = 'cnt\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.099 ns) + CELL(0.624 ns) 1.723 ns Add1~192 2 COMB LCCOMB_X19_Y8_N22 12 " "Info: 2: + IC(1.099 ns) + CELL(0.624 ns) = 1.723 ns; Loc. = LCCOMB_X19_Y8_N22; Fanout = 12; COMB Node = 'Add1~192'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.723 ns" { cnt[0] Add1~192 } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.589 ns) 3.075 ns dout~2191 3 COMB LCCOMB_X18_Y8_N30 1 " "Info: 3: + IC(0.763 ns) + CELL(0.589 ns) = 3.075 ns; Loc. = LCCOMB_X18_Y8_N30; Fanout = 1; COMB Node = 'dout~2191'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.352 ns" { Add1~192 dout~2191 } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.206 ns) 3.896 ns dout~2192 4 COMB LCCOMB_X17_Y8_N16 1 " "Info: 4: + IC(0.615 ns) + CELL(0.206 ns) = 3.896 ns; Loc. = LCCOMB_X17_Y8_N16; Fanout = 1; COMB Node = 'dout~2192'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.821 ns" { dout~2191 dout~2192 } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.460 ns) 5.656 ns dout\[3\]~reg0 5 REG LCFF_X18_Y9_N1 1 " "Info: 5: + IC(1.300 ns) + CELL(0.460 ns) = 5.656 ns; Loc. = LCFF_X18_Y9_N1; Fanout = 1; REG Node = 'dout\[3\]~reg0'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.760 ns" { dout~2192 dout[3]~reg0 } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.879 ns ( 33.22 % ) " "Info: Total cell delay = 1.879 ns ( 33.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.777 ns ( 66.78 % ) " "Info: Total interconnect delay = 3.777 ns ( 66.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.656 ns" { cnt[0] Add1~192 dout~2191 dout~2192 dout[3]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.656 ns" { cnt[0] Add1~192 dout~2191 dout~2192 dout[3]~reg0 } { 0.000ns 1.099ns 0.763ns 0.615ns 1.300ns } { 0.000ns 0.624ns 0.589ns 0.206ns 0.460ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns - Smallest " "Info: - Smallest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.753 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 78 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 78; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.666 ns) 2.753 ns dout\[3\]~reg0 3 REG LCFF_X18_Y9_N1 1 " "Info: 3: + IC(0.858 ns) + CELL(0.666 ns) = 2.753 ns; Loc. = LCFF_X18_Y9_N1; Fanout = 1; REG Node = 'dout\[3\]~reg0'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { clk~clkctrl dout[3]~reg0 } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.78 % ) " "Info: Total cell delay = 1.756 ns ( 63.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 36.22 % ) " "Info: Total interconnect delay = 0.997 ns ( 36.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { clk clk~clkctrl dout[3]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { clk clk~combout clk~clkctrl dout[3]~reg0 } { 0.000ns 0.000ns 0.139ns 0.858ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.755 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 78 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 78; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 2.755 ns cnt\[0\] 3 REG LCFF_X19_Y9_N19 26 " "Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.755 ns; Loc. = LCFF_X19_Y9_N19; Fanout = 26; REG Node = 'cnt\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { clk~clkctrl cnt[0] } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.74 % ) " "Info: Total cell delay = 1.756 ns ( 63.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 36.26 % ) " "Info: Total interconnect delay = 0.999 ns ( 36.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.755 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.755 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.139ns 0.860ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { clk clk~clkctrl dout[3]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { clk clk~combout clk~clkctrl dout[3]~reg0 } { 0.000ns 0.000ns 0.139ns 0.858ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.755 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.755 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.139ns 0.860ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.656 ns" { cnt[0] Add1~192 dout~2191 dout~2192 dout[3]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.656 ns" { cnt[0] Add1~192 dout~2191 dout~2192 dout[3]~reg0 } { 0.000ns 1.099ns 0.763ns 0.615ns 1.300ns } { 0.000ns 0.624ns 0.589ns 0.206ns 0.460ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { clk clk~clkctrl dout[3]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { clk clk~combout clk~clkctrl dout[3]~reg0 } { 0.000ns 0.000ns 0.139ns 0.858ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.755 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.755 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.139ns 0.860ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "stack\[5\]\[4\] push clk 8.740 ns register " "Info: tsu for register \"stack\[5\]\[4\]\" (data pin = \"push\", clock pin = \"clk\") is 8.740 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.582 ns + Longest pin register " "Info: + Longest pin to register delay is 11.582 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns push 1 PIN PIN_87 4 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_87; Fanout = 4; PIN Node = 'push'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { push } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.483 ns) + CELL(0.651 ns) 8.069 ns process0~1 2 COMB LCCOMB_X19_Y9_N26 7 " "Info: 2: + IC(6.483 ns) + CELL(0.651 ns) = 8.069 ns; Loc. = LCCOMB_X19_Y9_N26; Fanout = 7; COMB Node = 'process0~1'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.134 ns" { push process0~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.206 ns) 8.688 ns Decoder0~238 3 COMB LCCOMB_X19_Y9_N28 7 " "Info: 3: + IC(0.413 ns) + CELL(0.206 ns) = 8.688 ns; Loc. = LCCOMB_X19_Y9_N28; Fanout = 7; COMB Node = 'Decoder0~238'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.619 ns" { process0~1 Decoder0~238 } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.418 ns) + CELL(0.206 ns) 9.312 ns Decoder0~243 4 COMB LCCOMB_X19_Y9_N12 8 " "Info: 4: + IC(0.418 ns) + CELL(0.206 ns) = 9.312 ns; Loc. = LCCOMB_X19_Y9_N12; Fanout = 8; COMB Node = 'Decoder0~243'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.624 ns" { Decoder0~238 Decoder0~243 } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.415 ns) + CELL(0.855 ns) 11.582 ns stack\[5\]\[4\] 5 REG LCFF_X17_Y8_N1 1 " "Info: 5: + IC(1.415 ns) + CELL(0.855 ns) = 11.582 ns; Loc. = LCFF_X17_Y8_N1; Fanout = 1; REG Node = 'stack\[5\]\[4\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.270 ns" { Decoder0~243 stack[5][4] } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.853 ns ( 24.63 % ) " "Info: Total cell delay = 2.853 ns ( 24.63 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.729 ns ( 75.37 % ) " "Info: Total interconnect delay = 8.729 ns ( 75.37 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.582 ns" { push process0~1 Decoder0~238 Decoder0~243 stack[5][4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "11.582 ns" { push push~combout process0~1 Decoder0~238 Decoder0~243 stack[5][4] } { 0.000ns 0.000ns 6.483ns 0.413ns 0.418ns 1.415ns } { 0.000ns 0.935ns 0.651ns 0.206ns 0.206ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.802 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.802 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 78 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 78; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.666 ns) 2.802 ns stack\[5\]\[4\] 3 REG LCFF_X17_Y8_N1 1 " "Info: 3: + IC(0.907 ns) + CELL(0.666 ns) = 2.802 ns; Loc. = LCFF_X17_Y8_N1; Fanout = 1; REG Node = 'stack\[5\]\[4\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl stack[5][4] } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.67 % ) " "Info: Total cell delay = 1.756 ns ( 62.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.046 ns ( 37.33 % ) " "Info: Total interconnect delay = 1.046 ns ( 37.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.802 ns" { clk clk~clkctrl stack[5][4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.802 ns" { clk clk~combout clk~clkctrl stack[5][4] } { 0.000ns 0.000ns 0.139ns 0.907ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.582 ns" { push process0~1 Decoder0~238 Decoder0~243 stack[5][4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "11.582 ns" { push push~combout process0~1 Decoder0~238 Decoder0~243 stack[5][4] } { 0.000ns 0.000ns 6.483ns 0.413ns 0.418ns 1.415ns } { 0.000ns 0.935ns 0.651ns 0.206ns 0.206ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.802 ns" { clk clk~clkctrl stack[5][4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.802 ns" { clk clk~combout clk~clkctrl stack[5][4] } { 0.000ns 0.000ns 0.139ns 0.907ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[2\] dout\[2\]~reg0 8.897 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[2\]\" through register \"dout\[2\]~reg0\" is 8.897 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.753 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 78 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 78; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.666 ns) 2.753 ns dout\[2\]~reg0 3 REG LCFF_X18_Y9_N11 1 " "Info: 3: + IC(0.858 ns) + CELL(0.666 ns) = 2.753 ns; Loc. = LCFF_X18_Y9_N11; Fanout = 1; REG Node = 'dout\[2\]~reg0'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { clk~clkctrl dout[2]~reg0 } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.78 % ) " "Info: Total cell delay = 1.756 ns ( 63.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 36.22 % ) " "Info: Total interconnect delay = 0.997 ns ( 36.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { clk clk~clkctrl dout[2]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { clk clk~combout clk~clkctrl dout[2]~reg0 } { 0.000ns 0.000ns 0.139ns 0.858ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.840 ns + Longest register pin " "Info: + Longest register to pin delay is 5.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout\[2\]~reg0 1 REG LCFF_X18_Y9_N11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y9_N11; Fanout = 1; REG Node = 'dout\[2\]~reg0'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout[2]~reg0 } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.604 ns) + CELL(3.236 ns) 5.840 ns dout\[2\] 2 PIN PIN_51 0 " "Info: 2: + IC(2.604 ns) + CELL(3.236 ns) = 5.840 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'dout\[2\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.840 ns" { dout[2]~reg0 dout[2] } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 55.41 % ) " "Info: Total cell delay = 3.236 ns ( 55.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.604 ns ( 44.59 % ) " "Info: Total interconnect delay = 2.604 ns ( 44.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.840 ns" { dout[2]~reg0 dout[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.840 ns" { dout[2]~reg0 dout[2] } { 0.000ns 2.604ns } { 0.000ns 3.236ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { clk clk~clkctrl dout[2]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { clk clk~combout clk~clkctrl dout[2]~reg0 } { 0.000ns 0.000ns 0.139ns 0.858ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "5.840 ns" { dout[2]~reg0 dout[2] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "5.840 ns" { dout[2]~reg0 dout[2] } { 0.000ns 2.604ns } { 0.000ns 3.236ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "stack\[3\]\[4\] din\[4\] clk -0.114 ns register " "Info: th for register \"stack\[3\]\[4\]\" (data pin = \"din\[4\]\", clock pin = \"clk\") is -0.114 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.771 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.771 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 78 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 78; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(0.666 ns) 2.771 ns stack\[3\]\[4\] 3 REG LCFF_X18_Y8_N23 1 " "Info: 3: + IC(0.876 ns) + CELL(0.666 ns) = 2.771 ns; Loc. = LCFF_X18_Y8_N23; Fanout = 1; REG Node = 'stack\[3\]\[4\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.542 ns" { clk~clkctrl stack[3][4] } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.37 % ) " "Info: Total cell delay = 1.756 ns ( 63.37 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.015 ns ( 36.63 % ) " "Info: Total interconnect delay = 1.015 ns ( 36.63 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.771 ns" { clk clk~clkctrl stack[3][4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.771 ns" { clk clk~combout clk~clkctrl stack[3][4] } { 0.000ns 0.000ns 0.139ns 0.876ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.191 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns din\[4\] 1 PIN PIN_89 8 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_89; Fanout = 8; PIN Node = 'din\[4\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { din[4] } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.777 ns) + CELL(0.206 ns) 3.083 ns stack\[3\]\[4\]~feeder 2 COMB LCCOMB_X18_Y8_N22 1 " "Info: 2: + IC(1.777 ns) + CELL(0.206 ns) = 3.083 ns; Loc. = LCCOMB_X18_Y8_N22; Fanout = 1; COMB Node = 'stack\[3\]\[4\]~feeder'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.983 ns" { din[4] stack[3][4]~feeder } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.191 ns stack\[3\]\[4\] 3 REG LCFF_X18_Y8_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.191 ns; Loc. = LCFF_X18_Y8_N23; Fanout = 1; REG Node = 'stack\[3\]\[4\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { stack[3][4]~feeder stack[3][4] } "NODE_NAME" } } { "lifo.vhd" "" { Text "D:/my_eda/LIFO/lifo.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.414 ns ( 44.31 % ) " "Info: Total cell delay = 1.414 ns ( 44.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.777 ns ( 55.69 % ) " "Info: Total interconnect delay = 1.777 ns ( 55.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.191 ns" { din[4] stack[3][4]~feeder stack[3][4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.191 ns" { din[4] din[4]~combout stack[3][4]~feeder stack[3][4] } { 0.000ns 0.000ns 1.777ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.771 ns" { clk clk~clkctrl stack[3][4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.771 ns" { clk clk~combout clk~clkctrl stack[3][4] } { 0.000ns 0.000ns 0.139ns 0.876ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.191 ns" { din[4] stack[3][4]~feeder stack[3][4] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "3.191 ns" { din[4] din[4]~combout stack[3][4]~feeder stack[3][4] } { 0.000ns 0.000ns 1.777ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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