kn_cnt16.tan.rpt

在quartus开发环境下

; N/A   ; None         ; 5.175 ns   ; s    ; co~reg0   ; clk      ;
; N/A   ; None         ; 4.615 ns   ; d[1] ; q[1]~reg0 ; clk      ;
; N/A   ; None         ; 0.081 ns   ; d[3] ; q[3]~reg0 ; clk      ;
; N/A   ; None         ; -0.260 ns  ; d[2] ; q[2]~reg0 ; clk      ;
+-------+--------------+------------+------+-----------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 9.574 ns   ; q[3]~reg0 ; q[3] ; clk        ;
; N/A   ; None         ; 8.131 ns   ; q[0]~reg0 ; q[0] ; clk        ;
; N/A   ; None         ; 7.272 ns   ; q[1]~reg0 ; q[1] ; clk        ;
; N/A   ; None         ; 6.854 ns   ; q[2]~reg0 ; q[2] ; clk        ;
; N/A   ; None         ; 6.836 ns   ; co~reg0   ; co   ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; 0.526 ns  ; d[2] ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; 0.185 ns  ; d[3] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -4.349 ns ; d[1] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -4.874 ns ; s    ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -4.909 ns ; s    ; co~reg0   ; clk      ;
; N/A           ; None        ; -4.950 ns ; s    ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -4.950 ns ; s    ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -4.950 ns ; s    ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -4.993 ns ; d[0] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -5.279 ns ; en   ; co~reg0   ; clk      ;
; N/A           ; None        ; -5.366 ns ; updn ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -5.399 ns ; updn ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -5.399 ns ; updn ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -6.039 ns ; updn ; co~reg0   ; clk      ;
; N/A           ; None        ; -6.298 ns ; en   ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -6.298 ns ; en   ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -6.298 ns ; en   ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -6.298 ns ; en   ; q[2]~reg0 ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Mar 13 10:39:59 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off kn_cnt16 -c kn_cnt16 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 323.1 MHz between source register "q[0]~reg0" and destination register "q[3]~reg0" (period= 3.095 ns)
    Info: + Longest register to register delay is 2.831 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y9_N31; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: 2: + IC(0.457 ns) + CELL(0.596 ns) = 1.053 ns; Loc. = LCCOMB_X33_Y9_N20; Fanout = 2; COMB Node = 'Add0~102'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.139 ns; Loc. = LCCOMB_X33_Y9_N22; Fanout = 2; COMB Node = 'Add0~104'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.225 ns; Loc. = LCCOMB_X33_Y9_N24; Fanout = 1; COMB Node = 'Add0~106'
        Info: 5: + IC(0.000 ns) + CELL(0.506 ns) = 1.731 ns; Loc. = LCCOMB_X33_Y9_N26; Fanout = 1; COMB Node = 'Add0~107'
        Info: 6: + IC(0.376 ns) + CELL(0.616 ns) = 2.723 ns; Loc. = LCCOMB_X33_Y9_N14; Fanout = 1; COMB Node = 'q[3]~380'
        Info: 7: + IC(0.000 ns) + CELL(0.108 ns) = 2.831 ns; Loc. = LCFF_X33_Y9_N15; Fanout = 3; REG Node = 'q[3]~reg0'
        Info: Total cell delay = 1.998 ns ( 70.58 % )
        Info: Total interconnect delay = 0.833 ns ( 29.42 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.777 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.882 ns) + CELL(0.666 ns) = 2.777 ns; Loc. = LCFF_X33_Y9_N15; Fanout = 3; REG Node = 'q[3]~reg0'
            Info: Total cell delay = 1.756 ns ( 63.23 % )
            Info: Total interconnect delay = 1.021 ns ( 36.77 % )
        Info: - Longest clock path from clock "clk" to source register is 2.777 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.882 ns) + CELL(0.666 ns) = 2.777 ns; Loc. = LCFF_X33_Y9_N31; Fanout = 4; REG Node = 'q[0]~reg0'
            Info: Total cell delay = 1.756 ns ( 63.23 % )
            Info: Total interconnect delay = 1.021 ns ( 36.77 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q[3]~reg0" (data pin = "updn", clock pin = "clk") is 7.224 ns
    Info: + Longest pin to register delay is 10.041 ns
        Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_67; Fanout = 9; PIN Node = 'updn'
        Info: 2: + IC(6.819 ns) + CELL(0.596 ns) = 8.349 ns; Loc. = LCCOMB_X33_Y9_N22; Fanout = 2; COMB Node = 'Add0~104'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 8.435 ns; Loc. = LCCOMB_X33_Y9_N24; Fanout = 1; COMB Node = 'Add0~106'
        Info: 4: + IC(0.000 ns) + CELL(0.506 ns) = 8.941 ns; Loc. = LCCOMB_X33_Y9_N26; Fanout = 1; COMB Node = 'Add0~107'
        Info: 5: + IC(0.376 ns) + CELL(0.616 ns) = 9.933 ns; Loc. = LCCOMB_X33_Y9_N14; Fanout = 1; COMB Node = 'q[3]~380'
        Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 10.041 ns; Loc. = LCFF_X33_Y9_N15; Fanout = 3; REG Node = 'q[3]~reg0'
        Info: Total cell delay = 2.846 ns ( 28.34 % )
        Info: Total interconnect delay = 7.195 ns ( 71.66 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.777 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.882 ns) + CELL(0.666 ns) = 2.777 ns; Loc. = LCFF_X33_Y9_N15; Fanout = 3; REG Node = 'q[3]~reg0'
        Info: Total cell delay = 1.756 ns ( 63.23 % )
        Info: Total interconnect delay = 1.021 ns ( 36.77 % )
Info: tco from clock "clk" to destination pin "q[3]" through register "q[3]~reg0" is 9.574 ns
    Info: + Longest clock path from clock "clk" to source register is 2.777 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.882 ns) + CELL(0.666 ns) = 2.777 ns; Loc. = LCFF_X33_Y9_N15; Fanout = 3; REG Node = 'q[3]~reg0'
        Info: Total cell delay = 1.756 ns ( 63.23 % )
        Info: Total interconnect delay = 1.021 ns ( 36.77 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.493 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y9_N15; Fanout = 3; REG Node = 'q[3]~reg0'
        Info: 2: + IC(3.267 ns) + CELL(3.226 ns) = 6.493 ns; Loc. = PIN_59; Fanout = 0; PIN Node = 'q[3]'
        Info: Total cell delay = 3.226 ns ( 49.68 % )
        Info: Total interconnect delay = 3.267 ns ( 50.32 % )
Info: th for register "q[2]~reg0" (data pin = "d[2]", clock pin = "clk") is 0.526 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.777 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.882 ns) + CELL(0.666 ns) = 2.777 ns; Loc. = LCFF_X33_Y9_N11; Fanout = 4; REG Node = 'q[2]~reg0'
        Info: Total cell delay = 1.756 ns ( 63.23 % )
        Info: Total interconnect delay = 1.021 ns ( 36.77 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 2.557 ns
        Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'd[2]'
        Info: 2: + IC(0.987 ns) + CELL(0.460 ns) = 2.557 ns; Loc. = LCFF_X33_Y9_N11; Fanout = 4; REG Node = 'q[2]~reg0'
        Info: Total cell delay = 1.570 ns ( 61.40 % )
        Info: Total interconnect delay = 0.987 ns ( 38.60 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Mar 13 10:39:59 2007
    Info: Elapsed time: 00:00:02