kn_cnt16.vhd

来自「在quartus开发环境下」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity kn_cnt16 is
port(clk:in std_logic;
     clr:in std_logic;
     s:in std_logic;
     en:in std_logic;
     updn:in std_logic;
     co:out std_logic;
     d:in std_logic_vector(3 downto 0);
     q:buffer std_logic_vector(3 downto 0));
end;
architecture one of kn_cnt16 is
begin
process(clk,clr)
begin
if clr='1' then 
      q<="0000";
      co<='0';
elsif clk'event and clk='1' then
	if s='1' then q<=d;
	elsif en='1' then
		if updn='1' then
		   if q="1111" then q<="0000";co<='1';
		   else q<=q+1;co<='0';
		   end if;
		elsif updn='0' then
		   if q="0000" then q<="1111";co<='1';
		   else q<=q-1;co<='0';
		   end if;
		end if;
	end if;
end if;
end process;
end;