ty.vhd

来自「在quartus开发环境下」· VHDL 代码 · 共 10 行

library ieee;
use ieee.std_logic_1164.all;
entity or_2 is
port(a,b:in std_logic;
     c:out std_logic);
end;
architecture one of or_2 is
begin
c<= a or b;
end;