half_sub_1.vhd

在quartus开发环境下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity half_sub_1 is
port(a,b:in std_logic;
     dout,cout:out std_logic);
end;
architecture one of half_sub_1 is
signal temp:std_logic_vector(1 downto 0);
begin
temp<=('0'&a)-b;
dout<=temp(0);
cout<=temp(1);
end;