yb_cnt4.tan.qmsg

在quartus开发环境下

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register inst6 inst6 360.1 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 360.1 MHz between source register \"inst6\" and destination register \"inst6\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Longest register register " "Info: + Longest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst6 1 REG LCFF_X2_Y1_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'inst6'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { inst6 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns inst6~2 2 COMB LCCOMB_X2_Y1_N16 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X2_Y1_N16; Fanout = 1; COMB Node = 'inst6~2'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.393 ns" { inst6 inst6~2 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns inst6 3 REG LCFF_X2_Y1_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'inst6'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { inst6~2 inst6 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.501 ns" { inst6 inst6~2 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.501 ns" { inst6 inst6~2 inst6 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.230 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns clk 1 CLK PIN_47 1 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_47; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 200 -176 -8 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.970 ns) 3.225 ns inst 2 REG LCFF_X3_Y1_N9 3 " "Info: 2: + IC(1.311 ns) + CELL(0.970 ns) = 3.225 ns; Loc. = LCFF_X3_Y1_N9; Fanout = 3; REG Node = 'inst'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.281 ns" { clk inst } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 168 24 88 248 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.970 ns) 4.589 ns inst2 3 REG LCFF_X3_Y1_N15 3 " "Info: 3: + IC(0.394 ns) + CELL(0.970 ns) = 4.589 ns; Loc. = LCFF_X3_Y1_N15; Fanout = 3; REG Node = 'inst2'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.364 ns" { inst inst2 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 168 184 248 248 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.611 ns) + CELL(0.970 ns) 6.170 ns inst4 4 REG LCFF_X2_Y1_N9 3 " "Info: 4: + IC(0.611 ns) + CELL(0.970 ns) = 6.170 ns; Loc. = LCFF_X2_Y1_N9; Fanout = 3; REG Node = 'inst4'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { inst2 inst4 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 344 408 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.666 ns) 7.230 ns inst6 5 REG LCFF_X2_Y1_N17 2 " "Info: 5: + IC(0.394 ns) + CELL(0.666 ns) = 7.230 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'inst6'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.060 ns" { inst4 inst6 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.520 ns ( 62.52 % ) " "Info: Total cell delay = 4.520 ns ( 62.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.710 ns ( 37.48 % ) " "Info: Total interconnect delay = 2.710 ns ( 37.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { clk inst inst2 inst4 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { clk clk~combout inst inst2 inst4 inst6 } { 0.000ns 0.000ns 1.311ns 0.394ns 0.611ns 0.394ns } { 0.000ns 0.944ns 0.970ns 0.970ns 0.970ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.230 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns clk 1 CLK PIN_47 1 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_47; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 200 -176 -8 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.970 ns) 3.225 ns inst 2 REG LCFF_X3_Y1_N9 3 " "Info: 2: + IC(1.311 ns) + CELL(0.970 ns) = 3.225 ns; Loc. = LCFF_X3_Y1_N9; Fanout = 3; REG Node = 'inst'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.281 ns" { clk inst } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 168 24 88 248 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.970 ns) 4.589 ns inst2 3 REG LCFF_X3_Y1_N15 3 " "Info: 3: + IC(0.394 ns) + CELL(0.970 ns) = 4.589 ns; Loc. = LCFF_X3_Y1_N15; Fanout = 3; REG Node = 'inst2'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.364 ns" { inst inst2 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 168 184 248 248 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.611 ns) + CELL(0.970 ns) 6.170 ns inst4 4 REG LCFF_X2_Y1_N9 3 " "Info: 4: + IC(0.611 ns) + CELL(0.970 ns) = 6.170 ns; Loc. = LCFF_X2_Y1_N9; Fanout = 3; REG Node = 'inst4'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { inst2 inst4 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 344 408 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.666 ns) 7.230 ns inst6 5 REG LCFF_X2_Y1_N17 2 " "Info: 5: + IC(0.394 ns) + CELL(0.666 ns) = 7.230 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'inst6'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.060 ns" { inst4 inst6 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.520 ns ( 62.52 % ) " "Info: Total cell delay = 4.520 ns ( 62.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.710 ns ( 37.48 % ) " "Info: Total interconnect delay = 2.710 ns ( 37.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { clk inst inst2 inst4 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { clk clk~combout inst inst2 inst4 inst6 } { 0.000ns 0.000ns 1.311ns 0.394ns 0.611ns 0.394ns } { 0.000ns 0.944ns 0.970ns 0.970ns 0.970ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { clk inst inst2 inst4 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { clk clk~combout inst inst2 inst4 inst6 } { 0.000ns 0.000ns 1.311ns 0.394ns 0.611ns 0.394ns } { 0.000ns 0.944ns 0.970ns 0.970ns 0.970ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { clk inst inst2 inst4 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { clk clk~combout inst inst2 inst4 inst6 } { 0.000ns 0.000ns 1.311ns 0.394ns 0.611ns 0.394ns } { 0.000ns 0.944ns 0.970ns 0.970ns 0.970ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.501 ns" { inst6 inst6~2 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.501 ns" { inst6 inst6~2 inst6 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { clk inst inst2 inst4 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { clk clk~combout inst inst2 inst4 inst6 } { 0.000ns 0.000ns 1.311ns 0.394ns 0.611ns 0.394ns } { 0.000ns 0.944ns 0.970ns 0.970ns 0.970ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { clk inst inst2 inst4 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { clk clk~combout inst inst2 inst4 inst6 } { 0.000ns 0.000ns 1.311ns 0.394ns 0.611ns 0.394ns } { 0.000ns 0.944ns 0.970ns 0.970ns 0.970ns 0.666ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { inst6 } {  } {  } } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[3\] inst6 11.678 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[3\]\" through register \"inst6\" is 11.678 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.230 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns clk 1 CLK PIN_47 1 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_47; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 200 -176 -8 216 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.970 ns) 3.225 ns inst 2 REG LCFF_X3_Y1_N9 3 " "Info: 2: + IC(1.311 ns) + CELL(0.970 ns) = 3.225 ns; Loc. = LCFF_X3_Y1_N9; Fanout = 3; REG Node = 'inst'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "2.281 ns" { clk inst } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 168 24 88 248 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.970 ns) 4.589 ns inst2 3 REG LCFF_X3_Y1_N15 3 " "Info: 3: + IC(0.394 ns) + CELL(0.970 ns) = 4.589 ns; Loc. = LCFF_X3_Y1_N15; Fanout = 3; REG Node = 'inst2'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.364 ns" { inst inst2 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 168 184 248 248 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.611 ns) + CELL(0.970 ns) 6.170 ns inst4 4 REG LCFF_X2_Y1_N9 3 " "Info: 4: + IC(0.611 ns) + CELL(0.970 ns) = 6.170 ns; Loc. = LCFF_X2_Y1_N9; Fanout = 3; REG Node = 'inst4'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { inst2 inst4 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 344 408 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.666 ns) 7.230 ns inst6 5 REG LCFF_X2_Y1_N17 2 " "Info: 5: + IC(0.394 ns) + CELL(0.666 ns) = 7.230 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'inst6'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.060 ns" { inst4 inst6 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.520 ns ( 62.52 % ) " "Info: Total cell delay = 4.520 ns ( 62.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.710 ns ( 37.48 % ) " "Info: Total interconnect delay = 2.710 ns ( 37.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { clk inst inst2 inst4 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { clk clk~combout inst inst2 inst4 inst6 } { 0.000ns 0.000ns 1.311ns 0.394ns 0.611ns 0.394ns } { 0.000ns 0.944ns 0.970ns 0.970ns 0.970ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.144 ns + Longest register pin " "Info: + Longest register to pin delay is 4.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst6 1 REG LCFF_X2_Y1_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y1_N17; Fanout = 2; REG Node = 'inst6'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { inst6 } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { 176 496 560 256 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(3.236 ns) 4.144 ns q\[3\] 2 PIN PIN_43 0 " "Info: 2: + IC(0.908 ns) + CELL(3.236 ns) = 4.144 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'q\[3\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.144 ns" { inst6 q[3] } "NODE_NAME" } } { "yb_cnt4.bdf" "" { Schematic "D:/my_eda/yb_cnt4/yb_cnt4.bdf" { { -56 112 128 120 "q\[0\]" "" } { -56 264 280 120 "q\[1\]" "" } { -48 424 440 128 "q\[2\]" "" } { -48 568 584 128 "q\[3\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 78.09 % ) " "Info: Total cell delay = 3.236 ns ( 78.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.908 ns ( 21.91 % ) " "Info: Total interconnect delay = 0.908 ns ( 21.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.144 ns" { inst6 q[3] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.144 ns" { inst6 q[3] } { 0.000ns 0.908ns } { 0.000ns 3.236ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.230 ns" { clk inst inst2 inst4 inst6 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "7.230 ns" { clk clk~combout inst inst2 inst4 inst6 } { 0.000ns 0.000ns 1.311ns 0.394ns 0.611ns 0.394ns } { 0.000ns 0.944ns 0.970ns 0.970ns 0.970ns 0.666ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.144 ns" { inst6 q[3] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.144 ns" { inst6 q[3] } { 0.000ns 0.908ns } { 0.000ns 3.236ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 12 20:59:46 2007 " "Info: Processing ended: Mon Mar 12 20:59:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}