mux4.tan.qmsg

在quartus开发环境下

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 16:32:06 2007 " "Info: Processing started: Thu May 31 16:32:06 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off mux4 -c mux4 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux4 -c mux4 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[1\] y 13.346 ns Longest " "Info: Longest tpd from source pin \"a\[1\]\" to destination pin \"y\" is 13.346 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns a\[1\] 1 PIN PIN_42 2 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_42; Fanout = 2; PIN Node = 'a\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[1] } "NODE_NAME" } } { "mux4.vhd" "" { Text "D:/my_eda/mux4/mux4.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.280 ns) + CELL(0.206 ns) 7.430 ns Mux0~25 2 COMB LCCOMB_X1_Y9_N0 1 " "Info: 2: + IC(6.280 ns) + CELL(0.206 ns) = 7.430 ns; Loc. = LCCOMB_X1_Y9_N0; Fanout = 1; COMB Node = 'Mux0~25'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.486 ns" { a[1] Mux0~25 } "NODE_NAME" } } { "mux4.vhd" "" { Text "D:/my_eda/mux4/mux4.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.624 ns) 8.418 ns Mux0~26 3 COMB LCCOMB_X1_Y9_N18 1 " "Info: 3: + IC(0.364 ns) + CELL(0.624 ns) = 8.418 ns; Loc. = LCCOMB_X1_Y9_N18; Fanout = 1; COMB Node = 'Mux0~26'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.988 ns" { Mux0~25 Mux0~26 } "NODE_NAME" } } { "mux4.vhd" "" { Text "D:/my_eda/mux4/mux4.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.356 ns) + CELL(0.589 ns) 9.363 ns Mux0~27 4 COMB LCCOMB_X1_Y9_N16 1 " "Info: 4: + IC(0.356 ns) + CELL(0.589 ns) = 9.363 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 1; COMB Node = 'Mux0~27'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.945 ns" { Mux0~26 Mux0~27 } "NODE_NAME" } } { "mux4.vhd" "" { Text "D:/my_eda/mux4/mux4.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.927 ns) + CELL(3.056 ns) 13.346 ns y 5 PIN PIN_24 0 " "Info: 5: + IC(0.927 ns) + CELL(3.056 ns) = 13.346 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'y'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.983 ns" { Mux0~27 y } "NODE_NAME" } } { "mux4.vhd" "" { Text "D:/my_eda/mux4/mux4.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.419 ns ( 40.60 % ) " "Info: Total cell delay = 5.419 ns ( 40.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.927 ns ( 59.40 % ) " "Info: Total interconnect delay = 7.927 ns ( 59.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.346 ns" { a[1] Mux0~25 Mux0~26 Mux0~27 y } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.346 ns" { a[1] a[1]~combout Mux0~25 Mux0~26 Mux0~27 y } { 0.000ns 0.000ns 6.280ns 0.364ns 0.356ns 0.927ns } { 0.000ns 0.944ns 0.206ns 0.624ns 0.589ns 3.056ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 16:32:09 2007 " "Info: Processing ended: Thu May 31 16:32:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}