📄 yxbianma8_3_1.tan.rpt
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Timing Analyzer report for yxbianma8_3_1
Fri Mar 02 19:37:25 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.362 ns ; I2 ; Y0 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 13.362 ns ; I2 ; Y0 ;
; N/A ; None ; 13.243 ns ; I5 ; Y0 ;
; N/A ; None ; 13.226 ns ; I4 ; EO ;
; N/A ; None ; 13.173 ns ; I6 ; EO ;
; N/A ; None ; 13.170 ns ; I6 ; Y0 ;
; N/A ; None ; 12.997 ns ; I2 ; EO ;
; N/A ; None ; 12.948 ns ; I7 ; EO ;
; N/A ; None ; 12.913 ns ; I7 ; Y0 ;
; N/A ; None ; 12.807 ns ; I5 ; EO ;
; N/A ; None ; 12.501 ns ; I4 ; Y0 ;
; N/A ; None ; 12.494 ns ; I2 ; Y1 ;
; N/A ; None ; 12.342 ns ; I4 ; Y2 ;
; N/A ; None ; 12.289 ns ; I6 ; Y2 ;
; N/A ; None ; 12.261 ns ; I4 ; GS ;
; N/A ; None ; 12.208 ns ; I6 ; GS ;
; N/A ; None ; 12.064 ns ; I7 ; Y2 ;
; N/A ; None ; 11.999 ns ; I2 ; GS ;
; N/A ; None ; 11.983 ns ; I7 ; GS ;
; N/A ; None ; 11.957 ns ; I5 ; Y1 ;
; N/A ; None ; 11.923 ns ; I5 ; Y2 ;
; N/A ; None ; 11.842 ns ; I5 ; GS ;
; N/A ; None ; 11.634 ns ; I4 ; Y1 ;
; N/A ; None ; 11.310 ns ; I6 ; Y1 ;
; N/A ; None ; 11.062 ns ; I7 ; Y1 ;
; N/A ; None ; 7.865 ns ; I1 ; Y0 ;
; N/A ; None ; 7.854 ns ; EI ; Y0 ;
; N/A ; None ; 7.823 ns ; EI ; EO ;
; N/A ; None ; 7.737 ns ; I3 ; EO ;
; N/A ; None ; 7.622 ns ; I1 ; EO ;
; N/A ; None ; 7.295 ns ; I3 ; Y0 ;
; N/A ; None ; 7.036 ns ; I0 ; EO ;
; N/A ; None ; 6.825 ns ; EI ; GS ;
; N/A ; None ; 6.788 ns ; EI ; Y2 ;
; N/A ; None ; 6.739 ns ; I3 ; GS ;
; N/A ; None ; 6.624 ns ; I1 ; GS ;
; N/A ; None ; 6.424 ns ; I3 ; Y1 ;
; N/A ; None ; 6.368 ns ; EI ; Y1 ;
; N/A ; None ; 6.038 ns ; I0 ; GS ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Fri Mar 02 19:37:24 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off yxbianma8_3_1 -c yxbianma8_3_1 --timing_analysis_only
Info: Longest tpd from source pin "I2" to destination pin "Y0" is 13.362 ns
Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_113; Fanout = 3; PIN Node = 'I2'
Info: 2: + IC(6.307 ns) + CELL(0.624 ns) = 7.875 ns; Loc. = LCCOMB_X33_Y10_N22; Fanout = 1; COMB Node = '74148:inst|8~69'
Info: 3: + IC(0.367 ns) + CELL(0.206 ns) = 8.448 ns; Loc. = LCCOMB_X33_Y10_N24; Fanout = 1; COMB Node = '74148:inst|8~70'
Info: 4: + IC(1.688 ns) + CELL(3.226 ns) = 13.362 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'Y0'
Info: Total cell delay = 5.000 ns ( 37.42 % )
Info: Total interconnect delay = 8.362 ns ( 62.58 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Mar 02 19:37:25 2007
Info: Elapsed time: 00:00:03
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