📄 decoder3_8.tan.rpt
字号:
Classic Timing Analyzer report for decoder3_8
Thu May 31 16:07:30 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.210 ns ; g3 ; y[7] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 13.210 ns ; g3 ; y[7] ;
; N/A ; None ; 13.176 ns ; g2 ; y[7] ;
; N/A ; None ; 13.124 ns ; g3 ; y[2] ;
; N/A ; None ; 13.114 ns ; g3 ; y[0] ;
; N/A ; None ; 13.090 ns ; g2 ; y[2] ;
; N/A ; None ; 13.080 ns ; g2 ; y[0] ;
; N/A ; None ; 12.821 ns ; g3 ; y[6] ;
; N/A ; None ; 12.815 ns ; g3 ; y[3] ;
; N/A ; None ; 12.806 ns ; g3 ; y[5] ;
; N/A ; None ; 12.793 ns ; g3 ; y[1] ;
; N/A ; None ; 12.787 ns ; g2 ; y[6] ;
; N/A ; None ; 12.781 ns ; g2 ; y[3] ;
; N/A ; None ; 12.772 ns ; g2 ; y[5] ;
; N/A ; None ; 12.759 ns ; g2 ; y[1] ;
; N/A ; None ; 12.391 ns ; g3 ; y[4] ;
; N/A ; None ; 12.357 ns ; g2 ; y[4] ;
; N/A ; None ; 12.335 ns ; g1 ; y[7] ;
; N/A ; None ; 12.249 ns ; g1 ; y[2] ;
; N/A ; None ; 12.239 ns ; g1 ; y[0] ;
; N/A ; None ; 11.946 ns ; g1 ; y[6] ;
; N/A ; None ; 11.940 ns ; g1 ; y[3] ;
; N/A ; None ; 11.931 ns ; g1 ; y[5] ;
; N/A ; None ; 11.919 ns ; a[1] ; y[7] ;
; N/A ; None ; 11.918 ns ; g1 ; y[1] ;
; N/A ; None ; 11.880 ns ; a[0] ; y[7] ;
; N/A ; None ; 11.833 ns ; a[1] ; y[2] ;
; N/A ; None ; 11.823 ns ; a[1] ; y[0] ;
; N/A ; None ; 11.794 ns ; a[0] ; y[2] ;
; N/A ; None ; 11.791 ns ; a[0] ; y[0] ;
; N/A ; None ; 11.529 ns ; a[1] ; y[6] ;
; N/A ; None ; 11.524 ns ; a[1] ; y[3] ;
; N/A ; None ; 11.516 ns ; a[1] ; y[5] ;
; N/A ; None ; 11.516 ns ; g1 ; y[4] ;
; N/A ; None ; 11.503 ns ; a[1] ; y[1] ;
; N/A ; None ; 11.501 ns ; a[0] ; y[3] ;
; N/A ; None ; 11.494 ns ; a[0] ; y[6] ;
; N/A ; None ; 11.491 ns ; a[0] ; y[5] ;
; N/A ; None ; 11.482 ns ; a[0] ; y[1] ;
; N/A ; None ; 11.100 ns ; a[1] ; y[4] ;
; N/A ; None ; 11.074 ns ; a[0] ; y[4] ;
; N/A ; None ; 8.747 ns ; a[2] ; y[7] ;
; N/A ; None ; 8.615 ns ; a[2] ; y[2] ;
; N/A ; None ; 8.604 ns ; a[2] ; y[0] ;
; N/A ; None ; 8.359 ns ; a[2] ; y[6] ;
; N/A ; None ; 8.348 ns ; a[2] ; y[5] ;
; N/A ; None ; 8.306 ns ; a[2] ; y[3] ;
; N/A ; None ; 8.288 ns ; a[2] ; y[1] ;
; N/A ; None ; 7.932 ns ; a[2] ; y[4] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Thu May 31 16:07:27 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off decoder3_8 -c decoder3_8 --timing_analysis_only
Info: Longest tpd from source pin "g3" to destination pin "y[7]" is 13.210 ns
Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_103; Fanout = 1; PIN Node = 'g3'
Info: 2: + IC(6.831 ns) + CELL(0.319 ns) = 8.085 ns; Loc. = LCCOMB_X1_Y16_N0; Fanout = 8; COMB Node = 'y~194'
Info: 3: + IC(0.422 ns) + CELL(0.206 ns) = 8.713 ns; Loc. = LCCOMB_X1_Y16_N20; Fanout = 1; COMB Node = 'y~202'
Info: 4: + IC(1.261 ns) + CELL(3.236 ns) = 13.210 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'y[7]'
Info: Total cell delay = 4.696 ns ( 35.55 % )
Info: Total interconnect delay = 8.514 ns ( 64.45 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 103 megabytes of memory during processing
Info: Processing ended: Thu May 31 16:07:29 2007
Info: Elapsed time: 00:00:02
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -