decoder3_8.vht

在quartus开发环境下

	WAIT FOR 88920 ps;
	Y_expected(3) <= '1';
WAIT;
END PROCESS t_prcs_Y_3;
-- expected Y[2]
t_prcs_Y_2: PROCESS
BEGIN
	Y_expected(2) <= '1';
	WAIT FOR 179550 ps;
	Y_expected(2) <= '0';
	WAIT FOR 2626 ps;
	Y_expected(2) <= '1';
	WAIT FOR 180000 ps;
	Y_expected(2) <= '0';
	WAIT FOR 1127 ps;
	Y_expected(2) <= '1';
WAIT;
END PROCESS t_prcs_Y_2;
-- expected Y[1]
t_prcs_Y_1: PROCESS
BEGIN
	Y_expected(1) <= '1';
	WAIT FOR 182366 ps;
	Y_expected(1) <= '0';
	WAIT FOR 90000 ps;
	Y_expected(1) <= '1';
WAIT;
END PROCESS t_prcs_Y_1;
-- expected Y[0]
t_prcs_Y_0: PROCESS
BEGIN
	Y_expected(0) <= '1';
	WAIT FOR 362310 ps;
	Y_expected(0) <= '0';
WAIT;
END PROCESS t_prcs_Y_0;

-- Set trigger on real/expected o/ pattern changes                        

t_prcs_trigger_e : PROCESS(Y_expected)
BEGIN
	trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;

t_prcs_trigger_r : PROCESS(Y)
BEGIN
	trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;


t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;

VARIABLE last_Y_exp : STD_LOGIC_VECTOR(7 DOWNTO 0) := "UUUUUUUU";

VARIABLE on_first_change : trackvec := "1";
BEGIN

WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
	AND sampler'EVENT;
IF (debug_tbench = '1') THEN
	write(txt,string'("Scanning pattern "));
	write(txt,i);
	writeline(output,txt);
	write(txt,string'("| expected "));write(txt,Y_name);write(txt,string'(" = "));write(txt,Y_expected_prev);
	writeline(output,txt);
	write(txt,string'("| real "));write(txt,Y_name);write(txt,string'(" = "));write(txt,Y_prev);
	writeline(output,txt);
	i := i + 1;
END IF;
IF ( Y_expected_prev /= "XXXXXXXX" ) AND (Y_expected_prev /= "UUUUUUUU" ) AND (Y_prev /= Y_expected_prev) AND (
	(Y_expected_prev /= last_Y_exp) OR
	(on_first_change(1) = '1')
		) THEN
	throw_error("Y",Y_expected_prev,Y_prev);
	num_mismatches(0) <= num_mismatches(0) + 1;
	on_first_change(1) := '0';
	last_Y_exp := Y_expected_prev;
END IF;
    trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;


t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
	trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;

t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 1000000 ps;
total_mismatches := num_mismatches(0);
IF (total_mismatches = 0) THEN                                              
        write(txt,string'("Simulation passed !"));                        
        writeline(output,txt);                                              
ELSE                                                                        
        write(txt,total_mismatches);                                        
        write(txt,string'(" mismatched vectors : Simulation failed !"));  
        writeline(output,txt);                                              
END IF;                                                                     
WAIT;
END PROCESS t_prcs_endsim;

END ovec_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.decoder3_8_vhd_tb_types.ALL;                                         

ENTITY decoder3_8_vhd_vec_tst IS
END decoder3_8_vhd_vec_tst;
ARCHITECTURE decoder3_8_arch OF decoder3_8_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL a : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL g1 : STD_LOGIC;
SIGNAL g2 : STD_LOGIC;
SIGNAL g3 : STD_LOGIC;
SIGNAL Y : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sampler : sample_type;

COMPONENT decoder3_8
	PORT (
	a : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	g1 : IN STD_LOGIC;
	g2 : IN STD_LOGIC;
	g3 : IN STD_LOGIC;
	Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END COMPONENT;
COMPONENT decoder3_8_vhd_check_tst
PORT (
	Y : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	sampler : IN sample_type
);
END COMPONENT;
COMPONENT decoder3_8_vhd_sample_tst
PORT (
	a : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	g1 : IN STD_LOGIC;
	g2 : IN STD_LOGIC;
	g3 : IN STD_LOGIC;
	sampler : OUT sample_type
	);
END COMPONENT;
BEGIN
	i1 : decoder3_8
	PORT MAP (
-- list connections between master ports and signals
	a => a,
	g1 => g1,
	g2 => g2,
	g3 => g3,
	Y => Y
	);

-- g1
t_prcs_g1: PROCESS
BEGIN
	g1 <= '1';
	WAIT FOR 20000 ps;
	g1 <= '0';
	WAIT FOR 70000 ps;
	g1 <= '1';
WAIT;
END PROCESS t_prcs_g1;

-- g2
t_prcs_g2: PROCESS
BEGIN
	g2 <= '1';
	WAIT FOR 30000 ps;
	g2 <= '0';
WAIT;
END PROCESS t_prcs_g2;

-- g3
t_prcs_g3: PROCESS
BEGIN
	g3 <= '0';
	WAIT FOR 20000 ps;
	g3 <= '1';
	WAIT FOR 40000 ps;
	g3 <= '0';
WAIT;
END PROCESS t_prcs_g3;
-- a[2]
t_prcs_a_2: PROCESS
BEGIN
	a(2) <= '1';
	WAIT FOR 170000 ps;
	a(2) <= '0';
WAIT;
END PROCESS t_prcs_a_2;
-- a[1]
t_prcs_a_1: PROCESS
BEGIN
	a(1) <= '1';
	WAIT FOR 170000 ps;
	a(1) <= '0';
	WAIT FOR 90000 ps;
	a(1) <= '1';
	WAIT FOR 90000 ps;
	a(1) <= '0';
WAIT;
END PROCESS t_prcs_a_1;
-- a[0]
t_prcs_a_0: PROCESS
BEGIN
	a(0) <= '0';
	WAIT FOR 170000 ps;
	a(0) <= '1';
	WAIT FOR 180000 ps;
	a(0) <= '0';
WAIT;
END PROCESS t_prcs_a_0;
tb_sample : decoder3_8_vhd_sample_tst
PORT MAP (
	a => a,
	g1 => g1,
	g2 => g2,
	g3 => g3,
	sampler => sampler
	);

tb_out : decoder3_8_vhd_check_tst
PORT MAP (
	Y => Y,
	sampler => sampler
	);
END decoder3_8_arch;