decoder3_8.vht

在quartus开发环境下

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors     
-- are exported from a vector file in the Quartus Waveform Editor and apply to  
-- the top level entity of the current Quartus project .The user can use this   
-- testbench to simulate his design using a third-party simulation tool .       
-- *****************************************************************************
-- Generated on "05/16/2007 15:48:09"
                                                                        
-- Vhdl Self-Checking Test Bench (with test vectors) for design :       decoder3_8
-- 
-- Simulation tool : 3rd Party
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

PACKAGE decoder3_8_vhd_tb_types IS
-- input port types                                                       
-- output port names                                                     
CONSTANT Y_name : STRING (1 TO 1) := "Y";
-- n(outputs)                                                            
CONSTANT o_num : INTEGER := 1;
-- mismatches vector type                                                
TYPE mmvec IS ARRAY (0 to (o_num - 1)) OF INTEGER;
-- exp o/ first change track vector type                                     
TYPE trackvec IS ARRAY (1 to o_num) OF BIT;
-- sampler type                                                            
SUBTYPE sample_type IS STD_LOGIC;                                          
-- utility functions                                                     
FUNCTION std_logic_to_char (a: STD_LOGIC) RETURN CHARACTER;              
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR) RETURN STRING; 
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);                                               
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);                                        
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC);                                   
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR);                     

END decoder3_8_vhd_tb_types;

PACKAGE BODY decoder3_8_vhd_tb_types IS
        FUNCTION std_logic_to_char (a: STD_LOGIC)  
                RETURN CHARACTER IS                
        BEGIN                                      
        CASE a IS                                  
         WHEN 'U' =>                               
          RETURN 'U';                              
         WHEN 'X' =>                               
          RETURN 'X';                              
         WHEN '0' =>                               
          RETURN '0';                              
         WHEN '1' =>                               
          RETURN '1';                              
         WHEN 'Z' =>                               
          RETURN 'Z';                              
         WHEN 'W' =>                               
          RETURN 'W';                              
         WHEN 'L' =>                               
          RETURN 'L';                              
         WHEN 'H' =>                               
          RETURN 'H';                              
         WHEN '-' =>                               
          RETURN 'D';                              
        END CASE;                                  
        END;                                       

        FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR)       
                RETURN STRING IS                                        
        VARIABLE result : STRING(1 TO a'LENGTH);                        
        VARIABLE j : NATURAL := 1;                                      
        BEGIN                                                           
                FOR i IN a'RANGE LOOP                                   
                        result(j) := std_logic_to_char(a(i));           
                        j := j + 1;                                     
                END LOOP;                                               
                RETURN result;                                          
        END;                                                            

        PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:=RIGHT; field:IN WIDTH:=0) IS 
        BEGIN                                                           
                write(L,std_logic_to_char(VALUE),JUSTIFIED,field);      
        END;                                                            
                                                                        
        PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0) IS                           
        BEGIN                                                               
                write(L,std_logic_vector_to_string(VALUE),JUSTIFIED,field); 
        END;                                                                

        PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC) IS                               
        VARIABLE txt : LINE;                                              
        BEGIN                                                             
        write(txt,string'("ERROR! Vector Mismatch for output port "));  
        write(txt,output_port_name);                                      
        write(txt,string'(" :: @time = "));                             
        write(txt,NOW);                                                   
        write(txt,string'(", Expected value = "));                      
        write(txt,expected_value);                                        
        write(txt,string'(", Real value = "));                          
        write(txt,real_value);                                            
        writeline(output,txt);                                            
        END;                                                              

        PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR) IS                 
        VARIABLE txt : LINE;                                              
        BEGIN                                                             
        write(txt,string'("ERROR! Vector Mismatch for output port "));  
        write(txt,output_port_name);                                      
        write(txt,string'(" :: @time = "));                             
        write(txt,NOW);                                                   
        write(txt,string'(", Expected value = "));                      
        write(txt,expected_value);                                        
        write(txt,string'(", Real value = "));                          
        write(txt,real_value);                                            
        writeline(output,txt);                                            
        END;                                                              

END decoder3_8_vhd_tb_types;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

USE WORK.decoder3_8_vhd_tb_types.ALL;                                         

ENTITY decoder3_8_vhd_sample_tst IS
PORT (
	a : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	g1 : IN STD_LOGIC;
	g2 : IN STD_LOGIC;
	g3 : IN STD_LOGIC;
	sampler : OUT sample_type
	);
END decoder3_8_vhd_sample_tst;

ARCHITECTURE sample_arch OF decoder3_8_vhd_sample_tst IS
SIGNAL tbo_int_sample_clk : sample_type := '1';
BEGIN
t_prcs_sample : PROCESS ( a , g1 , g2 , g3 )
BEGIN
	IF (NOW > 0 ps) AND (NOW < 1000000 ps) THEN
		tbo_int_sample_clk <= NOT tbo_int_sample_clk ;
	END IF;
END PROCESS t_prcs_sample;
sampler <= tbo_int_sample_clk;
END sample_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.decoder3_8_vhd_tb_types.ALL;                                         

ENTITY decoder3_8_vhd_check_tst IS 
GENERIC (
	debug_tbench : BIT := '0'
);
PORT (
	Y : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	sampler : IN sample_type
);
END decoder3_8_vhd_check_tst;
ARCHITECTURE ovec_arch OF decoder3_8_vhd_check_tst IS
SIGNAL Y_expected,Y_expected_prev,Y_prev : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);

BEGIN

-- Update history buffers  expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger) 
BEGIN
	Y_expected_prev <= Y_expected;
END PROCESS t_prcs_update_o_expected_hist;


-- Update history buffers  real /o
t_prcs_update_o_real_hist : PROCESS (trigger) 
BEGIN
	Y_prev <= Y;
END PROCESS t_prcs_update_o_real_hist;


-- expected Y[7]
t_prcs_Y_7: PROCESS
BEGIN
	Y_expected(7) <= '1';
WAIT;
END PROCESS t_prcs_Y_7;
-- expected Y[6]
t_prcs_Y_6: PROCESS
BEGIN
	Y_expected(6) <= '1';
	WAIT FOR 103060 ps;
	Y_expected(6) <= '0';
	WAIT FOR 75816 ps;
	Y_expected(6) <= '1';
WAIT;
END PROCESS t_prcs_Y_6;
-- expected Y[5]
t_prcs_Y_5: PROCESS
BEGIN
	Y_expected(5) <= '1';
WAIT;
END PROCESS t_prcs_Y_5;
-- expected Y[4]
t_prcs_Y_4: PROCESS
BEGIN
	Y_expected(4) <= '1';
WAIT;
END PROCESS t_prcs_Y_4;
-- expected Y[3]
t_prcs_Y_3: PROCESS
BEGIN
	Y_expected(3) <= '1';
	WAIT FOR 181135 ps;
	Y_expected(3) <= '0';
	WAIT FOR 1080 ps;
	Y_expected(3) <= '1';
	WAIT FOR 90000 ps;
	Y_expected(3) <= '0';