decoder3_8_1.map.rpt

在quartus开发环境下

; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                              ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                              ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
; decoder3_8_1.bdf                 ; yes             ; User Block Diagram/Schematic File  ; D:/my_eda/decoder3_8_1/decoder3_8_1.bdf                   ;
; 74138.bdf                        ; yes             ; Megafunction                       ; e:/altera60/quartus60/libraries/others/maxplus2/74138.bdf ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+


+---------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                   ;
+---------------------------------------------+-----------------+
; Resource                                    ; Usage           ;
+---------------------------------------------+-----------------+
; Estimated Total logic elements              ; 9               ;
; Total combinational functions               ; 9               ;
; Logic element usage by number of LUT inputs ;                 ;
;     -- 4 input functions                    ; 8               ;
;     -- 3 input functions                    ; 1               ;
;     -- <=2 input functions                  ; 0               ;
;         -- Combinational cells for routing  ; 0               ;
; Logic elements by mode                      ;                 ;
;     -- normal mode                          ; 9               ;
;     -- arithmetic mode                      ; 0               ;
; Total registers                             ; 0               ;
; I/O pins                                    ; 14              ;
; Maximum fan-out node                        ; 74138:inst|1~13 ;
; Maximum fan-out                             ; 8               ;
; Total fan-out                               ; 43              ;
; Average fan-out                             ; 1.87            ;
+---------------------------------------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                      ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name      ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------+
; |decoder3_8_1              ; 9 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 14   ; 0            ; |decoder3_8_1            ;
;    |74138:inst|            ; 9 (9)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |decoder3_8_1|74138:inst ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Mar 03 14:26:40 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off decoder3_8_1 -c decoder3_8_1
Info: Found 1 design units, including 1 entities, in source file decoder3_8_1.bdf
    Info: Found entity 1: decoder3_8_1
Info: Elaborating entity "decoder3_8_1" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file e:/altera60/quartus60/libraries/others/maxplus2/74138.bdf
    Info: Found entity 1: 74138
Info: Elaborating entity "74138" for hierarchy "74138:inst"
Info: Elaborated megafunction instantiation "74138:inst"
Info: Implemented 23 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 8 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Mar 03 14:26:43 2007
    Info: Elapsed time: 00:00:05