📄 decoder3_8_1.tan.rpt
字号:
Timing Analyzer report for decoder3_8_1
Sat Mar 03 14:27:14 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.693 ns ; G3 ; Y6 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 13.693 ns ; G3 ; Y6 ;
; N/A ; None ; 13.202 ns ; A2 ; Y6 ;
; N/A ; None ; 13.088 ns ; G3 ; Y3 ;
; N/A ; None ; 13.088 ns ; G3 ; Y1 ;
; N/A ; None ; 13.055 ns ; G2 ; Y6 ;
; N/A ; None ; 13.023 ns ; G3 ; Y0 ;
; N/A ; None ; 12.903 ns ; A1 ; Y6 ;
; N/A ; None ; 12.667 ns ; G3 ; Y7 ;
; N/A ; None ; 12.527 ns ; A2 ; Y3 ;
; N/A ; None ; 12.503 ns ; A2 ; Y1 ;
; N/A ; None ; 12.450 ns ; G2 ; Y3 ;
; N/A ; None ; 12.450 ns ; G2 ; Y1 ;
; N/A ; None ; 12.433 ns ; A2 ; Y0 ;
; N/A ; None ; 12.405 ns ; G3 ; Y4 ;
; N/A ; None ; 12.398 ns ; G3 ; Y5 ;
; N/A ; None ; 12.385 ns ; G2 ; Y0 ;
; N/A ; None ; 12.311 ns ; A1 ; Y3 ;
; N/A ; None ; 12.269 ns ; A0 ; Y6 ;
; N/A ; None ; 12.230 ns ; G3 ; Y2 ;
; N/A ; None ; 12.184 ns ; A1 ; Y1 ;
; N/A ; None ; 12.176 ns ; A2 ; Y7 ;
; N/A ; None ; 12.118 ns ; A1 ; Y0 ;
; N/A ; None ; 12.029 ns ; G2 ; Y7 ;
; N/A ; None ; 11.916 ns ; A2 ; Y4 ;
; N/A ; None ; 11.902 ns ; A2 ; Y5 ;
; N/A ; None ; 11.880 ns ; A1 ; Y7 ;
; N/A ; None ; 11.767 ns ; G2 ; Y4 ;
; N/A ; None ; 11.760 ns ; G2 ; Y5 ;
; N/A ; None ; 11.669 ns ; A0 ; Y3 ;
; N/A ; None ; 11.665 ns ; A2 ; Y2 ;
; N/A ; None ; 11.663 ns ; A0 ; Y1 ;
; N/A ; None ; 11.598 ns ; A0 ; Y0 ;
; N/A ; None ; 11.592 ns ; G2 ; Y2 ;
; N/A ; None ; 11.511 ns ; A1 ; Y4 ;
; N/A ; None ; 11.501 ns ; A1 ; Y5 ;
; N/A ; None ; 11.448 ns ; A1 ; Y2 ;
; N/A ; None ; 11.241 ns ; A0 ; Y7 ;
; N/A ; None ; 10.986 ns ; A0 ; Y4 ;
; N/A ; None ; 10.976 ns ; A0 ; Y5 ;
; N/A ; None ; 10.813 ns ; A0 ; Y2 ;
; N/A ; None ; 9.776 ns ; G1 ; Y6 ;
; N/A ; None ; 9.171 ns ; G1 ; Y3 ;
; N/A ; None ; 9.171 ns ; G1 ; Y1 ;
; N/A ; None ; 9.106 ns ; G1 ; Y0 ;
; N/A ; None ; 8.750 ns ; G1 ; Y7 ;
; N/A ; None ; 8.488 ns ; G1 ; Y4 ;
; N/A ; None ; 8.481 ns ; G1 ; Y5 ;
; N/A ; None ; 8.313 ns ; G1 ; Y2 ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Sat Mar 03 14:27:14 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off decoder3_8_1 -c decoder3_8_1 --timing_analysis_only
Info: Longest tpd from source pin "G3" to destination pin "Y6" is 13.693 ns
Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_141; Fanout = 1; PIN Node = 'G3'
Info: 2: + IC(6.337 ns) + CELL(0.651 ns) = 7.922 ns; Loc. = LCCOMB_X1_Y2_N26; Fanout = 8; COMB Node = '74138:inst|1~13'
Info: 3: + IC(0.419 ns) + CELL(0.202 ns) = 8.543 ns; Loc. = LCCOMB_X1_Y2_N10; Fanout = 1; COMB Node = '74138:inst|21'
Info: 4: + IC(1.914 ns) + CELL(3.236 ns) = 13.693 ns; Loc. = PIN_51; Fanout = 0; PIN Node = 'Y6'
Info: Total cell delay = 5.023 ns ( 36.68 % )
Info: Total interconnect delay = 8.670 ns ( 63.32 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Mar 03 14:27:14 2007
Info: Elapsed time: 00:00:02
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