nor_2.fit.rpt

在quartus开发环境下

; Number of Distinct Inputs  (Average = 2.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve nCEO pin after configuration         ; As output driving ground ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                         ;
+------------------------------------------------------------------+------------+
; Name                                                             ; Value      ;
+------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1                                 ; ff         ;
; Mid Wire Use - Fit Attempt 1                                     ; 0          ;
; Mid Slack - Fit Attempt 1                                        ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1                              ; 2          ;
; LE/ALM Count - Fit Attempt 1                                     ; 2          ;
; LAB Count - Fit Attempt 1                                        ; 2          ;
; Outputs per Lab - Fit Attempt 1                                  ; 0.500      ;
; Inputs per LAB - Fit Attempt 1                                   ; 1.000      ;
; Global Inputs per LAB - Fit Attempt 1                            ; 0.000      ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1    ; 0:2        ;
; LAB Constraint 'non-global controls' - Fit Attempt 1             ; 0:2        ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1               ; 0:2        ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1       ; 0:2        ;
; LAB Constraint 'global controls' - Fit Attempt 1                 ; 0:2        ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2        ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2        ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1      ; 0:2        ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1                 ; 0:2        ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1          ; 0:2        ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1      ; 0:2        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1        ; 0:2        ;
; LEs in Chains - Fit Attempt 1                                    ; 0          ;
; LEs in Long Chains - Fit Attempt 1                               ; 0          ;
; LABs with Chains - Fit Attempt 1                                 ; 0          ;
; LABs with Multiple Chains - Fit Attempt 1                        ; 0          ;
; Time - Fit Attempt 1                                             ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1                              ; 0.016      ;
+------------------------------------------------------------------+------------+


+-----------------------------------------------+
; Advanced Data - Placement                     ;
+----------------------------------+------------+
; Name                             ; Value      ;
+----------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff         ;
; Early Wire Use - Fit Attempt 1   ; 0          ;
; Early Slack - Fit Attempt 1      ; 2147483639 ;
; Auto Fit Point 3 - Fit Attempt 1 ; ff         ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff         ;
; Mid Wire Use - Fit Attempt 1     ; 0          ;
; Mid Slack - Fit Attempt 1        ; 2147483639 ;
; Late Wire Use - Fit Attempt 1    ; 0          ;
; Late Slack - Fit Attempt 1       ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff         ;
; Time - Fit Attempt 1             ; 0          ;
+----------------------------------+------------+


+--------------------------------------------------+
; Advanced Data - Routing                          ;
+-------------------------------------+------------+
; Name                                ; Value      ;
+-------------------------------------+------------+
; Early Slack - Fit Attempt 1         ; 2147483639 ;
; Mid Slack - Fit Attempt 1           ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Wire Use - Fit Attempt 1       ; 0          ;
; Time - Fit Attempt 1                ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016      ;
+-------------------------------------+------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Feb 12 21:59:52 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off nor_2 -c nor_2
Info: Selected device EP2C8T144C8 for design "nor_2"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: No exact pin location assignment(s) for 3 pins of 3 total pins
    Info: Pin y not assigned to an exact location on the device
    Info: Pin b not assigned to an exact location on the device
    Info: Pin a not assigned to an exact location on the device
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 3 (unused VREF, 3.30 VCCIO, 2 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  15 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  20 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 1 output pins without output pin load capacitance assignment
    Info: Pin "y" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Feb 12 21:59:58 2007
    Info: Elapsed time: 00:00:07


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/my_eda/nor/nor_2.fit.smsg.