add.fit.rpt

在quartus开发环境下

I/O Assignment Analysis report for add
Sat May 12 22:53:26 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. I/O Assignment Analysis Summary
  3. Fitter Messages
  4. Pin-Out File
  5. I/O Bank Usage
  6. All Package Pins
  7. Output Pin Default Load For Reported TCO
  8. I/O Assignment Analysis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; I/O Assignment Analysis Summary                                          ;
+--------------------------------+-----------------------------------------+
; I/O Assignment Analysis Status ; Successful - Sat May 12 22:53:25 2007   ;
; Quartus II Version             ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name                  ; add                                     ;
; Top-level Entity Name          ; add                                     ;
; Family                         ; Cyclone II                              ;
; Device                         ; EP2C8T144C8                             ;
; Timing Models                  ; Final                                   ;
; Total pins                     ; 0 / 85 ( 0 % )                          ;
; Total virtual pins             ; 0                                       ;
; Total PLLs                     ; 0 / 2 ( 0 % )                           ;
+--------------------------------+-----------------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat May 12 22:53:19 2007
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off add -c add --check_ios
Warning: Analysis and Synthesis (quartus_map) with top-level entity name "add" was not run before running I/O Assignment Analysis -- I/O Assignment Analysis will check only I/O assignments on the reserved pins
Info: Selected device EP2C8T144C8 for design "add"
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "a" is assigned to location or region, but does not exist in design
    Warning: Node "b" is assigned to location or region, but does not exist in design
    Warning: Node "ci" is assigned to location or region, but does not exist in design
    Warning: Node "co" is assigned to location or region, but does not exist in design
    Warning: Node "s" is assigned to location or region, but does not exist in design
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II I/O Assignment Analysis was successful. 0 errors, 8 warnings
    Info: Allocated 147 megabytes of memory during processing
    Info: Processing ended: Sat May 12 22:53:25 2007
    Info: Elapsed time: 00:00:06


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/my_eda/add/add.pin.


+-----------------------------------------------------------+
; I/O Bank Usage                                            ;
+----------+-----------------+---------------+--------------+
; I/O Bank ; Usage           ; VCCIO Voltage ; VREF Voltage ;
+----------+-----------------+---------------+--------------+
; 1        ; 2 / 17 ( 12 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 23 ( 0 % )  ; 3.3V          ; --           ;
; 3        ; 1 / 21 ( 5 % )  ; 3.3V          ; --           ;
; 4        ; 0 / 24 ( 0 % )  ; 3.3V          ; --           ;
+----------+-----------------+---------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                       ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                           ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+