cnt24.tan.rpt

在quartus开发环境下

; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[3] ; one_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.506 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[3] ; one_temp[1] ; clk        ; clk      ; None                        ; None                      ; 2.501 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[3] ; ten_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.439 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[3] ; ten_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.353 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[1] ; ten_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.350 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[3] ; one_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.309 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[3] ; ten_temp[1] ; clk        ; clk      ; None                        ; None                      ; 2.307 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[3] ; one_temp[1] ; clk        ; clk      ; None                        ; None                      ; 2.304 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[3] ; one_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.303 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[1] ; ten_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.264 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[0] ; ten_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.188 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[0] ; ten_temp[0] ; clk        ; clk      ; None                        ; None                      ; 2.132 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[2] ; one_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.121 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[2] ; ten_temp[1] ; clk        ; clk      ; None                        ; None                      ; 2.119 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[2] ; one_temp[1] ; clk        ; clk      ; None                        ; None                      ; 2.116 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[2] ; one_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.115 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[1] ; ten_temp[0] ; clk        ; clk      ; None                        ; None                      ; 2.113 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[0] ; ten_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.102 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[2] ; ten_temp[0] ; clk        ; clk      ; None                        ; None                      ; 1.949 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[3] ; ten_temp[0] ; clk        ; clk      ; None                        ; None                      ; 1.789 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[0] ; one_temp[2] ; clk        ; clk      ; None                        ; None                      ; 1.694 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[0] ; one_temp[1] ; clk        ; clk      ; None                        ; None                      ; 1.689 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[0] ; one_temp[3] ; clk        ; clk      ; None                        ; None                      ; 1.688 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[2] ; ten_temp[3] ; clk        ; clk      ; None                        ; None                      ; 1.661 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[0] ; ten_temp[0] ; clk        ; clk      ; None                        ; None                      ; 1.539 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[3] ; ten_temp[3] ; clk        ; clk      ; None                        ; None                      ; 1.241 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; ten_temp[2] ; ten_temp[2] ; clk        ; clk      ; None                        ; None                      ; 1.182 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[0] ; one_temp[0] ; clk        ; clk      ; None                        ; None                      ; 0.501 ns                ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 9.157 ns   ; ten_temp[1] ; co     ; clk        ;
; N/A   ; None         ; 8.850 ns   ; one_temp[2] ; co     ; clk        ;
; N/A   ; None         ; 8.601 ns   ; one_temp[3] ; co     ; clk        ;
; N/A   ; None         ; 8.516 ns   ; one_temp[1] ; co     ; clk        ;
; N/A   ; None         ; 8.404 ns   ; ten_temp[3] ; co     ; clk        ;
; N/A   ; None         ; 8.371 ns   ; one_temp[0] ; co     ; clk        ;
; N/A   ; None         ; 8.318 ns   ; ten_temp[0] ; ten[0] ; clk        ;
; N/A   ; None         ; 8.216 ns   ; ten_temp[2] ; co     ; clk        ;
; N/A   ; None         ; 8.059 ns   ; ten_temp[1] ; ten[1] ; clk        ;
; N/A   ; None         ; 7.789 ns   ; ten_temp[0] ; co     ; clk        ;
; N/A   ; None         ; 7.747 ns   ; one_temp[3] ; one[3] ; clk        ;
; N/A   ; None         ; 7.655 ns   ; one_temp[1] ; one[1] ; clk        ;
; N/A   ; None         ; 7.342 ns   ; one_temp[2] ; one[2] ; clk        ;
; N/A   ; None         ; 7.311 ns   ; one_temp[0] ; one[0] ; clk        ;
; N/A   ; None         ; 7.063 ns   ; ten_temp[2] ; ten[2] ; clk        ;
; N/A   ; None         ; 7.053 ns   ; ten_temp[3] ; ten[3] ; clk        ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jun 01 09:53:28 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cnt24 -c cnt24 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 275.63 MHz between source register "one_temp[0]" and destination register "ten_temp[1]" (period= 3.628 ns)
    Info: + Longest register to register delay is 3.364 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N9; Fanout = 6; REG Node = 'one_temp[0]'
        Info: 2: + IC(0.449 ns) + CELL(0.571 ns) = 1.020 ns; Loc. = LCCOMB_X1_Y2_N30; Fanout = 5; COMB Node = 'Equal2~36'
        Info: 3: + IC(0.380 ns) + CELL(0.596 ns) = 1.996 ns; Loc. = LCCOMB_X1_Y2_N18; Fanout = 2; COMB Node = 'Add0~49'
        Info: 4: + IC(0.000 ns) + CELL(0.506 ns) = 2.502 ns; Loc. = LCCOMB_X1_Y2_N20; Fanout = 1; COMB Node = 'Add0~50'
        Info: 5: + IC(0.384 ns) + CELL(0.370 ns) = 3.256 ns; Loc. = LCCOMB_X1_Y2_N26; Fanout = 1; COMB Node = 'ten_temp~55'
        Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 3.364 ns; Loc. = LCFF_X1_Y2_N27; Fanout = 4; REG Node = 'ten_temp[1]'
        Info: Total cell delay = 2.151 ns ( 63.94 % )
        Info: Total interconnect delay = 1.213 ns ( 36.06 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.816 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N27; Fanout = 4; REG Node = 'ten_temp[1]'
            Info: Total cell delay = 1.756 ns ( 62.36 % )
            Info: Total interconnect delay = 1.060 ns ( 37.64 % )
        Info: - Longest clock path from clock "clk" to source register is 2.816 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N9; Fanout = 6; REG Node = 'one_temp[0]'
            Info: Total cell delay = 1.756 ns ( 62.36 % )
            Info: Total interconnect delay = 1.060 ns ( 37.64 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "co" through register "ten_temp[1]" is 9.157 ns
    Info: + Longest clock path from clock "clk" to source register is 2.816 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N27; Fanout = 4; REG Node = 'ten_temp[1]'
        Info: Total cell delay = 1.756 ns ( 62.36 % )
        Info: Total interconnect delay = 1.060 ns ( 37.64 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.037 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N27; Fanout = 4; REG Node = 'ten_temp[1]'
        Info: 2: + IC(1.719 ns) + CELL(0.615 ns) = 2.334 ns; Loc. = LCCOMB_X1_Y2_N6; Fanout = 5; COMB Node = 'process0~0'
        Info: 3: + IC(0.647 ns) + CELL(3.056 ns) = 6.037 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'co'
        Info: Total cell delay = 3.671 ns ( 60.81 % )
        Info: Total interconnect delay = 2.366 ns ( 39.19 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Fri Jun 01 09:53:30 2007
    Info: Elapsed time: 00:00:02