cnt24.tan.rpt

在quartus开发环境下

Classic Timing Analyzer report for cnt24
Fri Jun 01 09:53:30 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                    ;
+------------------------------+-------+---------------+----------------------------------+-------------+-------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From        ; To          ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------+-------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 9.157 ns                         ; ten_temp[1] ; co          ; clk        ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 275.63 MHz ( period = 3.628 ns ) ; one_temp[0] ; ten_temp[1] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;             ;             ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------+-------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                             ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From        ; To          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 275.63 MHz ( period = 3.628 ns )               ; one_temp[0] ; ten_temp[1] ; clk        ; clk      ; None                        ; None                      ; 3.364 ns                ;
; N/A   ; 277.09 MHz ( period = 3.609 ns )               ; one_temp[1] ; ten_temp[1] ; clk        ; clk      ; None                        ; None                      ; 3.345 ns                ;
; N/A   ; 290.28 MHz ( period = 3.445 ns )               ; one_temp[2] ; ten_temp[1] ; clk        ; clk      ; None                        ; None                      ; 3.181 ns                ;
; N/A   ; 300.66 MHz ( period = 3.326 ns )               ; ten_temp[1] ; one_temp[2] ; clk        ; clk      ; None                        ; None                      ; 3.062 ns                ;
; N/A   ; 300.84 MHz ( period = 3.324 ns )               ; ten_temp[1] ; ten_temp[1] ; clk        ; clk      ; None                        ; None                      ; 3.060 ns                ;
; N/A   ; 301.11 MHz ( period = 3.321 ns )               ; ten_temp[1] ; one_temp[1] ; clk        ; clk      ; None                        ; None                      ; 3.057 ns                ;
; N/A   ; 301.20 MHz ( period = 3.320 ns )               ; ten_temp[1] ; one_temp[3] ; clk        ; clk      ; None                        ; None                      ; 3.056 ns                ;
; N/A   ; 304.41 MHz ( period = 3.285 ns )               ; one_temp[3] ; ten_temp[1] ; clk        ; clk      ; None                        ; None                      ; 3.021 ns                ;
; N/A   ; 321.13 MHz ( period = 3.114 ns )               ; one_temp[0] ; one_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.850 ns                ;
; N/A   ; 321.23 MHz ( period = 3.113 ns )               ; one_temp[0] ; one_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.849 ns                ;
; N/A   ; 323.10 MHz ( period = 3.095 ns )               ; one_temp[1] ; one_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.831 ns                ;
; N/A   ; 323.21 MHz ( period = 3.094 ns )               ; one_temp[1] ; one_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.830 ns                ;
; N/A   ; 328.30 MHz ( period = 3.046 ns )               ; one_temp[0] ; ten_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.782 ns                ;
; N/A   ; 328.73 MHz ( period = 3.042 ns )               ; one_temp[0] ; one_temp[1] ; clk        ; clk      ; None                        ; None                      ; 2.778 ns                ;
; N/A   ; 329.60 MHz ( period = 3.034 ns )               ; ten_temp[0] ; ten_temp[1] ; clk        ; clk      ; None                        ; None                      ; 2.770 ns                ;
; N/A   ; 330.36 MHz ( period = 3.027 ns )               ; one_temp[1] ; ten_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.763 ns                ;
; N/A   ; 330.80 MHz ( period = 3.023 ns )               ; one_temp[1] ; one_temp[1] ; clk        ; clk      ; None                        ; None                      ; 2.759 ns                ;
; N/A   ; 331.24 MHz ( period = 3.019 ns )               ; one_temp[2] ; one_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.755 ns                ;
; N/A   ; 331.79 MHz ( period = 3.014 ns )               ; one_temp[2] ; one_temp[1] ; clk        ; clk      ; None                        ; None                      ; 2.750 ns                ;
; N/A   ; 331.90 MHz ( period = 3.013 ns )               ; one_temp[2] ; one_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.749 ns                ;
; N/A   ; 337.84 MHz ( period = 2.960 ns )               ; one_temp[0] ; ten_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.696 ns                ;
; N/A   ; 340.02 MHz ( period = 2.941 ns )               ; one_temp[1] ; ten_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.677 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[2] ; ten_temp[3] ; clk        ; clk      ; None                        ; None                      ; 2.599 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[2] ; ten_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.513 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; one_temp[3] ; one_temp[2] ; clk        ; clk      ; None                        ; None                      ; 2.507 ns                ;