cnt24.tan.qmsg

在quartus开发环境下

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register one_temp\[0\] register ten_temp\[1\] 275.63 MHz 3.628 ns Internal " "Info: Clock \"clk\" has Internal fmax of 275.63 MHz between source register \"one_temp\[0\]\" and destination register \"ten_temp\[1\]\" (period= 3.628 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.364 ns + Longest register register " "Info: + Longest register to register delay is 3.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns one_temp\[0\] 1 REG LCFF_X1_Y2_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N9; Fanout = 6; REG Node = 'one_temp\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { one_temp[0] } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.571 ns) 1.020 ns Equal2~36 2 COMB LCCOMB_X1_Y2_N30 5 " "Info: 2: + IC(0.449 ns) + CELL(0.571 ns) = 1.020 ns; Loc. = LCCOMB_X1_Y2_N30; Fanout = 5; COMB Node = 'Equal2~36'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.020 ns" { one_temp[0] Equal2~36 } "NODE_NAME" } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.380 ns) + CELL(0.596 ns) 1.996 ns Add0~49 3 COMB LCCOMB_X1_Y2_N18 2 " "Info: 3: + IC(0.380 ns) + CELL(0.596 ns) = 1.996 ns; Loc. = LCCOMB_X1_Y2_N18; Fanout = 2; COMB Node = 'Add0~49'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.976 ns" { Equal2~36 Add0~49 } "NODE_NAME" } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.502 ns Add0~50 4 COMB LCCOMB_X1_Y2_N20 1 " "Info: 4: + IC(0.000 ns) + CELL(0.506 ns) = 2.502 ns; Loc. = LCCOMB_X1_Y2_N20; Fanout = 1; COMB Node = 'Add0~50'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~49 Add0~50 } "NODE_NAME" } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.370 ns) 3.256 ns ten_temp~55 5 COMB LCCOMB_X1_Y2_N26 1 " "Info: 5: + IC(0.384 ns) + CELL(0.370 ns) = 3.256 ns; Loc. = LCCOMB_X1_Y2_N26; Fanout = 1; COMB Node = 'ten_temp~55'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.754 ns" { Add0~50 ten_temp~55 } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.364 ns ten_temp\[1\] 6 REG LCFF_X1_Y2_N27 4 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 3.364 ns; Loc. = LCFF_X1_Y2_N27; Fanout = 4; REG Node = 'ten_temp\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { ten_temp~55 ten_temp[1] } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.151 ns ( 63.94 % ) " "Info: Total cell delay = 2.151 ns ( 63.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.213 ns ( 36.06 % ) " "Info: Total interconnect delay = 1.213 ns ( 36.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.364 ns" { one_temp[0] Equal2~36 Add0~49 Add0~50 ten_temp~55 ten_temp[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.364 ns" { one_temp[0] Equal2~36 Add0~49 Add0~50 ten_temp~55 ten_temp[1] } { 0.000ns 0.449ns 0.380ns 0.000ns 0.384ns 0.000ns } { 0.000ns 0.571ns 0.596ns 0.506ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.816 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.816 ns ten_temp\[1\] 3 REG LCFF_X1_Y2_N27 4 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N27; Fanout = 4; REG Node = 'ten_temp\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl ten_temp[1] } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.36 % ) " "Info: Total cell delay = 1.756 ns ( 62.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 37.64 % ) " "Info: Total interconnect delay = 1.060 ns ( 37.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl ten_temp[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl ten_temp[1] } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.816 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.816 ns one_temp\[0\] 3 REG LCFF_X1_Y2_N9 6 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N9; Fanout = 6; REG Node = 'one_temp\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl one_temp[0] } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.36 % ) " "Info: Total cell delay = 1.756 ns ( 62.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 37.64 % ) " "Info: Total interconnect delay = 1.060 ns ( 37.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl one_temp[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl one_temp[0] } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl ten_temp[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl ten_temp[1] } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl one_temp[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl one_temp[0] } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.364 ns" { one_temp[0] Equal2~36 Add0~49 Add0~50 ten_temp~55 ten_temp[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.364 ns" { one_temp[0] Equal2~36 Add0~49 Add0~50 ten_temp~55 ten_temp[1] } { 0.000ns 0.449ns 0.380ns 0.000ns 0.384ns 0.000ns } { 0.000ns 0.571ns 0.596ns 0.506ns 0.370ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl ten_temp[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl ten_temp[1] } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl one_temp[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl one_temp[0] } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk co ten_temp\[1\] 9.157 ns register " "Info: tco from clock \"clk\" to destination pin \"co\" through register \"ten_temp\[1\]\" is 9.157 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.816 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.921 ns) + CELL(0.666 ns) 2.816 ns ten_temp\[1\] 3 REG LCFF_X1_Y2_N27 4 " "Info: 3: + IC(0.921 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X1_Y2_N27; Fanout = 4; REG Node = 'ten_temp\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { clk~clkctrl ten_temp[1] } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.36 % ) " "Info: Total cell delay = 1.756 ns ( 62.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.060 ns ( 37.64 % ) " "Info: Total interconnect delay = 1.060 ns ( 37.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl ten_temp[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl ten_temp[1] } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.037 ns + Longest register pin " "Info: + Longest register to pin delay is 6.037 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ten_temp\[1\] 1 REG LCFF_X1_Y2_N27 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N27; Fanout = 4; REG Node = 'ten_temp\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ten_temp[1] } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.719 ns) + CELL(0.615 ns) 2.334 ns process0~0 2 COMB LCCOMB_X1_Y2_N6 5 " "Info: 2: + IC(1.719 ns) + CELL(0.615 ns) = 2.334 ns; Loc. = LCCOMB_X1_Y2_N6; Fanout = 5; COMB Node = 'process0~0'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { ten_temp[1] process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.647 ns) + CELL(3.056 ns) 6.037 ns co 3 PIN PIN_30 0 " "Info: 3: + IC(0.647 ns) + CELL(3.056 ns) = 6.037 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'co'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.703 ns" { process0~0 co } "NODE_NAME" } } { "cnt24.vhd" "" { Text "D:/my_eda/cnt24/cnt24.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.671 ns ( 60.81 % ) " "Info: Total cell delay = 3.671 ns ( 60.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.366 ns ( 39.19 % ) " "Info: Total interconnect delay = 2.366 ns ( 39.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.037 ns" { ten_temp[1] process0~0 co } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.037 ns" { ten_temp[1] process0~0 co } { 0.000ns 1.719ns 0.647ns } { 0.000ns 0.615ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl ten_temp[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl ten_temp[1] } { 0.000ns 0.000ns 0.139ns 0.921ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.037 ns" { ten_temp[1] process0~0 co } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.037 ns" { ten_temp[1] process0~0 co } { 0.000ns 1.719ns 0.647ns } { 0.000ns 0.615ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 01 09:53:30 2007 " "Info: Processing ended: Fri Jun 01 09:53:30 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}