cnt24.vhd

在quartus开发环境下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt24 is
port(clk,clr:in std_logic;
     ten,one:out std_logic_vector(3 downto 0);
     co:out std_logic);
end;
architecture one of cnt24 is
	signal ten_temp,one_temp:std_logic_vector(3 downto 0);
begin
process(clk,clr)
begin
	if clr='1' then 
	   ten_temp<="0000";
	   one_temp<="0000";
	elsif clk'event and clk='1' then
	   if  ten_temp=2 and one_temp=3 then 
	             ten_temp<="0000";
	             one_temp<="0000";
	   elsif one_temp=9 then
	             one_temp<="0000"; 
	             ten_temp<=ten_temp+1;
	   else one_temp<=one_temp+1;
	   end if;
	end if;
end process;
	ten<=ten_temp;
	one<=one_temp;
	co<='1' when ten_temp=2 and one_temp=3 else '0'; 
end;