xor_2_1.vhd

在quartus开发环境下

library ieee;
use ieee.std_logic_1164.all;
entity xor_2_1 is
port(a,b:in std_logic;
     y:out std_logic);
end;
architecture one of xor_2_1 is
signal ab :std_logic_vector(1 downto 0);
begin
ab<=a&b;
process(ab)is
begin
 case ab is
	when "00"=>y<='0';
	when "01"=>y<='1';
	when "10"=>y<='1';
	when "11"=>y<='0';
	when others=>null;
 end case;
end process;
end;