lifo_1.map.qmsg

在quartus开发环境下

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 05 16:15:25 2007 " "Info: Processing started: Thu Apr 05 16:15:25 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LIFO_1 -c LIFO_1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LIFO_1 -c LIFO_1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LIFO_1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file LIFO_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lifo_1-one " "Info: Found design unit 1: lifo_1-one" {  } { { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lifo_1 " "Info: Found entity 1: lifo_1" {  } { { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "LIFO_1 " "Info: Elaborating entity \"LIFO_1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VRFC_INDEX_SIGNAL_NOT_WIDE_ENOUGH" "LIFO_1.vhd(30) " "Warning (10027): Verilog HDL or VHDL warning at LIFO_1.vhd(30): index signal is not wide enough to address all bits of range" {  } { { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 30 0 0 } }  } 0 10027 "Verilog HDL or VHDL warning at %1!s!: index signal is not wide enough to address all bits of range" 0 0}
{ "Warning" "WVRFX_L2_VRFC_INDEX_SIGNAL_NOT_WIDE_ENOUGH" "LIFO_1.vhd(39) " "Warning (10027): Verilog HDL or VHDL warning at LIFO_1.vhd(39): index signal is not wide enough to address all bits of range" {  } { { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 39 0 0 } }  } 0 10027 "Verilog HDL or VHDL warning at %1!s!: index signal is not wide enough to address all bits of range" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Allocated 141 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 05 16:15:29 2007 " "Info: Processing ended: Thu Apr 05 16:15:29 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IQSYN_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 0 "*******************************************************************" 0 0}
{ "Info" "IQSYN_START_BANNER_PRODUCT" "Partition Merge Quartus II " "Info: Running Quartus II Partition Merge" { { "Info" "IQSYN_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQSYN_START_BANNER_TIME" "Thu Apr 05 16:15:29 2007 " "Info: Processing started: Thu Apr 05 16:15:29 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 0 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "155 " "Info: Implemented 155 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "133 " "Info: Implemented 133 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQSYN_ERROR_COUNT" "Partition Merge 0 s 0 s Quartus II " "Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings" { { "Info" "IQSYN_END_BANNER_TIME" "Thu Apr 05 16:15:30 2007 " "Info: Processing ended: Thu Apr 05 16:15:30 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQSYN_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}