📄 lifo_1.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[0\] register dout\[7\]~reg0 130.87 MHz 7.641 ns Internal " "Info: Clock \"clk\" has Internal fmax of 130.87 MHz between source register \"cnt\[0\]\" and destination register \"dout\[7\]~reg0\" (period= 7.641 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.373 ns + Longest register register " "Info: + Longest register to register delay is 7.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LCFF_X19_Y9_N15 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y9_N15; Fanout = 18; REG Node = 'cnt\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.692 ns) + CELL(0.623 ns) 1.315 ns Add1~65 2 COMB LCCOMB_X18_Y9_N6 12 " "Info: 2: + IC(0.692 ns) + CELL(0.623 ns) = 1.315 ns; Loc. = LCCOMB_X18_Y9_N6; Fanout = 12; COMB Node = 'Add1~65'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.315 ns" { cnt[0] Add1~65 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.101 ns) + CELL(0.624 ns) 3.040 ns dout~1183 3 COMB LCCOMB_X18_Y9_N14 1 " "Info: 3: + IC(1.101 ns) + CELL(0.624 ns) = 3.040 ns; Loc. = LCCOMB_X18_Y9_N14; Fanout = 1; COMB Node = 'dout~1183'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.725 ns" { Add1~65 dout~1183 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.206 ns) 4.341 ns dout~1184 4 COMB LCCOMB_X18_Y8_N12 1 " "Info: 4: + IC(1.095 ns) + CELL(0.206 ns) = 4.341 ns; Loc. = LCCOMB_X18_Y8_N12; Fanout = 1; COMB Node = 'dout~1184'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.301 ns" { dout~1183 dout~1184 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.318 ns) + CELL(0.206 ns) 5.865 ns dout~1185 5 COMB LCCOMB_X17_Y10_N0 1 " "Info: 5: + IC(1.318 ns) + CELL(0.206 ns) = 5.865 ns; Loc. = LCCOMB_X17_Y10_N0; Fanout = 1; COMB Node = 'dout~1185'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { dout~1184 dout~1185 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 6.436 ns dout~1186 6 COMB LCCOMB_X17_Y10_N14 1 " "Info: 6: + IC(0.365 ns) + CELL(0.206 ns) = 6.436 ns; Loc. = LCCOMB_X17_Y10_N14; Fanout = 1; COMB Node = 'dout~1186'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { dout~1185 dout~1186 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.623 ns) + CELL(0.206 ns) 7.265 ns dout~1187 7 COMB LCCOMB_X18_Y10_N4 1 " "Info: 7: + IC(0.623 ns) + CELL(0.206 ns) = 7.265 ns; Loc. = LCCOMB_X18_Y10_N4; Fanout = 1; COMB Node = 'dout~1187'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.829 ns" { dout~1186 dout~1187 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.373 ns dout\[7\]~reg0 8 REG LCFF_X18_Y10_N5 1 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 7.373 ns; Loc. = LCFF_X18_Y10_N5; Fanout = 1; REG Node = 'dout\[7\]~reg0'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { dout~1187 dout[7]~reg0 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.179 ns ( 29.55 % ) " "Info: Total cell delay = 2.179 ns ( 29.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.194 ns ( 70.45 % ) " "Info: Total interconnect delay = 5.194 ns ( 70.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.373 ns" { cnt[0] Add1~65 dout~1183 dout~1184 dout~1185 dout~1186 dout~1187 dout[7]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "7.373 ns" { cnt[0] Add1~65 dout~1183 dout~1184 dout~1185 dout~1186 dout~1187 dout[7]~reg0 } { 0.000ns 0.692ns 1.101ns 1.095ns 1.318ns 0.365ns 0.623ns 0.000ns } { 0.000ns 0.623ns 0.624ns 0.206ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.751 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.666 ns) 2.751 ns dout\[7\]~reg0 3 REG LCFF_X18_Y10_N5 1 " "Info: 3: + IC(0.856 ns) + CELL(0.666 ns) = 2.751 ns; Loc. = LCFF_X18_Y10_N5; Fanout = 1; REG Node = 'dout\[7\]~reg0'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.522 ns" { clk~clkctrl dout[7]~reg0 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.83 % ) " "Info: Total cell delay = 1.756 ns ( 63.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.995 ns ( 36.17 % ) " "Info: Total interconnect delay = 0.995 ns ( 36.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.751 ns" { clk clk~clkctrl dout[7]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.751 ns" { clk clk~combout clk~clkctrl dout[7]~reg0 } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.755 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.666 ns) 2.755 ns cnt\[0\] 3 REG LCFF_X19_Y9_N15 18 " "Info: 3: + IC(0.860 ns) + CELL(0.666 ns) = 2.755 ns; Loc. = LCFF_X19_Y9_N15; Fanout = 18; REG Node = 'cnt\[0\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { clk~clkctrl cnt[0] } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.74 % ) " "Info: Total cell delay = 1.756 ns ( 63.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 36.26 % ) " "Info: Total interconnect delay = 0.999 ns ( 36.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.755 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.755 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.139ns 0.860ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.751 ns" { clk clk~clkctrl dout[7]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.751 ns" { clk clk~combout clk~clkctrl dout[7]~reg0 } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.755 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.755 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.139ns 0.860ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.373 ns" { cnt[0] Add1~65 dout~1183 dout~1184 dout~1185 dout~1186 dout~1187 dout[7]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "7.373 ns" { cnt[0] Add1~65 dout~1183 dout~1184 dout~1185 dout~1186 dout~1187 dout[7]~reg0 } { 0.000ns 0.692ns 1.101ns 1.095ns 1.318ns 0.365ns 0.623ns 0.000ns } { 0.000ns 0.623ns 0.624ns 0.206ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.751 ns" { clk clk~clkctrl dout[7]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.751 ns" { clk clk~combout clk~clkctrl dout[7]~reg0 } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.755 ns" { clk clk~clkctrl cnt[0] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.755 ns" { clk clk~combout clk~clkctrl cnt[0] } { 0.000ns 0.000ns 0.139ns 0.860ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "stack\[6\]\[5\] push clk 9.072 ns register " "Info: tsu for register \"stack\[6\]\[5\]\" (data pin = \"push\", clock pin = \"clk\") is 9.072 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.865 ns + Longest pin register " "Info: + Longest pin to register delay is 11.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns push 1 PIN PIN_135 4 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_135; Fanout = 4; PIN Node = 'push'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { push } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.954 ns) + CELL(0.370 ns) 8.268 ns stack\[7\]\[1\]~2211 2 COMB LCCOMB_X16_Y10_N16 9 " "Info: 2: + IC(6.954 ns) + CELL(0.370 ns) = 8.268 ns; Loc. = LCCOMB_X16_Y10_N16; Fanout = 9; COMB Node = 'stack\[7\]\[1\]~2211'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "7.324 ns" { push stack[7][1]~2211 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.475 ns) + CELL(0.206 ns) 9.949 ns Decoder0~100 3 COMB LCCOMB_X18_Y9_N16 8 " "Info: 3: + IC(1.475 ns) + CELL(0.206 ns) = 9.949 ns; Loc. = LCCOMB_X18_Y9_N16; Fanout = 8; COMB Node = 'Decoder0~100'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { stack[7][1]~2211 Decoder0~100 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.061 ns) + CELL(0.855 ns) 11.865 ns stack\[6\]\[5\] 4 REG LCFF_X19_Y10_N7 1 " "Info: 4: + IC(1.061 ns) + CELL(0.855 ns) = 11.865 ns; Loc. = LCFF_X19_Y10_N7; Fanout = 1; REG Node = 'stack\[6\]\[5\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.916 ns" { Decoder0~100 stack[6][5] } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.375 ns ( 20.02 % ) " "Info: Total cell delay = 2.375 ns ( 20.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.490 ns ( 79.98 % ) " "Info: Total interconnect delay = 9.490 ns ( 79.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.865 ns" { push stack[7][1]~2211 Decoder0~100 stack[6][5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "11.865 ns" { push push~combout stack[7][1]~2211 Decoder0~100 stack[6][5] } { 0.000ns 0.000ns 6.954ns 1.475ns 1.061ns } { 0.000ns 0.944ns 0.370ns 0.206ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.753 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.666 ns) 2.753 ns stack\[6\]\[5\] 3 REG LCFF_X19_Y10_N7 1 " "Info: 3: + IC(0.858 ns) + CELL(0.666 ns) = 2.753 ns; Loc. = LCFF_X19_Y10_N7; Fanout = 1; REG Node = 'stack\[6\]\[5\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { clk~clkctrl stack[6][5] } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.78 % ) " "Info: Total cell delay = 1.756 ns ( 63.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 36.22 % ) " "Info: Total interconnect delay = 0.997 ns ( 36.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { clk clk~clkctrl stack[6][5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { clk clk~combout clk~clkctrl stack[6][5] } { 0.000ns 0.000ns 0.139ns 0.858ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.865 ns" { push stack[7][1]~2211 Decoder0~100 stack[6][5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "11.865 ns" { push push~combout stack[7][1]~2211 Decoder0~100 stack[6][5] } { 0.000ns 0.000ns 6.954ns 1.475ns 1.061ns } { 0.000ns 0.944ns 0.370ns 0.206ns 0.855ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { clk clk~clkctrl stack[6][5] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { clk clk~combout clk~clkctrl stack[6][5] } { 0.000ns 0.000ns 0.139ns 0.858ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[6\] dout\[6\]~reg0 9.181 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[6\]\" through register \"dout\[6\]~reg0\" is 9.181 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.751 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.666 ns) 2.751 ns dout\[6\]~reg0 3 REG LCFF_X18_Y10_N11 1 " "Info: 3: + IC(0.856 ns) + CELL(0.666 ns) = 2.751 ns; Loc. = LCFF_X18_Y10_N11; Fanout = 1; REG Node = 'dout\[6\]~reg0'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.522 ns" { clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.83 % ) " "Info: Total cell delay = 1.756 ns ( 63.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.995 ns ( 36.17 % ) " "Info: Total interconnect delay = 0.995 ns ( 36.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.751 ns" { clk clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.751 ns" { clk clk~combout clk~clkctrl dout[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.126 ns + Longest register pin " "Info: + Longest register to pin delay is 6.126 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout\[6\]~reg0 1 REG LCFF_X18_Y10_N11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y10_N11; Fanout = 1; REG Node = 'dout\[6\]~reg0'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout[6]~reg0 } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(3.226 ns) 6.126 ns dout\[6\] 2 PIN PIN_119 0 " "Info: 2: + IC(2.900 ns) + CELL(3.226 ns) = 6.126 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'dout\[6\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.126 ns" { dout[6]~reg0 dout[6] } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.226 ns ( 52.66 % ) " "Info: Total cell delay = 3.226 ns ( 52.66 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 47.34 % ) " "Info: Total interconnect delay = 2.900 ns ( 47.34 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.126 ns" { dout[6]~reg0 dout[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.126 ns" { dout[6]~reg0 dout[6] } { 0.000ns 2.900ns } { 0.000ns 3.226ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.751 ns" { clk clk~clkctrl dout[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.751 ns" { clk clk~combout clk~clkctrl dout[6]~reg0 } { 0.000ns 0.000ns 0.139ns 0.856ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "6.126 ns" { dout[6]~reg0 dout[6] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "6.126 ns" { dout[6]~reg0 dout[6] } { 0.000ns 2.900ns } { 0.000ns 3.226ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "stack\[7\]\[3\] din\[3\] clk 0.134 ns register " "Info: th for register \"stack\[7\]\[3\]\" (data pin = \"din\[3\]\", clock pin = \"clk\") is 0.134 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.753 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'clk~clkctrl'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.666 ns) 2.753 ns stack\[7\]\[3\] 3 REG LCFF_X19_Y10_N27 1 " "Info: 3: + IC(0.858 ns) + CELL(0.666 ns) = 2.753 ns; Loc. = LCFF_X19_Y10_N27; Fanout = 1; REG Node = 'stack\[7\]\[3\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { clk~clkctrl stack[7][3] } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.78 % ) " "Info: Total cell delay = 1.756 ns ( 63.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 36.22 % ) " "Info: Total interconnect delay = 0.997 ns ( 36.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { clk clk~clkctrl stack[7][3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { clk clk~combout clk~clkctrl stack[7][3] } { 0.000ns 0.000ns 0.139ns 0.858ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.925 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns din\[3\] 1 PIN PIN_88 8 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 8; PIN Node = 'din\[3\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { din[3] } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.206 ns) 2.817 ns stack\[7\]\[3\]~feeder 2 COMB LCCOMB_X19_Y10_N26 1 " "Info: 2: + IC(1.501 ns) + CELL(0.206 ns) = 2.817 ns; Loc. = LCCOMB_X19_Y10_N26; Fanout = 1; COMB Node = 'stack\[7\]\[3\]~feeder'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.707 ns" { din[3] stack[7][3]~feeder } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.925 ns stack\[7\]\[3\] 3 REG LCFF_X19_Y10_N27 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.925 ns; Loc. = LCFF_X19_Y10_N27; Fanout = 1; REG Node = 'stack\[7\]\[3\]'" { } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { stack[7][3]~feeder stack[7][3] } "NODE_NAME" } } { "LIFO_1.vhd" "" { Text "D:/my_eda/LIFO_1/LIFO_1.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.424 ns ( 48.68 % ) " "Info: Total cell delay = 1.424 ns ( 48.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.501 ns ( 51.32 % ) " "Info: Total interconnect delay = 1.501 ns ( 51.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { din[3] stack[7][3]~feeder stack[7][3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { din[3] din[3]~combout stack[7][3]~feeder stack[7][3] } { 0.000ns 0.000ns 1.501ns 0.000ns } { 0.000ns 1.110ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.753 ns" { clk clk~clkctrl stack[7][3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.753 ns" { clk clk~combout clk~clkctrl stack[7][3] } { 0.000ns 0.000ns 0.139ns 0.858ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus ii7.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { din[3] stack[7][3]~feeder stack[7][3] } "NODE_NAME" } } { "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus ii7.0/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { din[3] din[3]~combout stack[7][3]~feeder stack[7][3] } { 0.000ns 0.000ns 1.501ns 0.000ns } { 0.000ns 1.110ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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