lifo_1.vhd

在quartus开发环境下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lifo_1 is
port(clr:in std_logic;------清零信号
     push:in std_logic;-----压栈
     pop:in std_logic;------出栈
     clk:in std_logic;------时钟
     din:in std_logic_vector(7 downto 0);-------数据输入端
     empty:out std_logic;-----------------------栈空信号
     full:out std_logic;------------------------栈满信号
     dout:out std_logic_vector(7 downto 0));----数据输出端
end;
architecture one of lifo_1 is
	type memory is array(0 to 15)of std_logic_vector(7 downto 0);---存储空间
begin
process(clk,clr)
	variable stack:memory;
	variable x:std_logic;-------------------栈满信号标志位
	variable cnt:integer range 0 to 7;-----指针信号，栈底指针为0
begin
if clr='1' then----------------清零
           dout<=(others=>'0');
           x:='0';
           cnt:=0;
elsif clk'event and clk='1' then     
	if push='1' and pop='0' and x='0' then-------------压栈
	    if cnt/=7 then
		   empty<='0'; 
		   stack(cnt):=din;------存入数据
		   cnt:=cnt+1;-----------指针加1
		else 
		   stack(7):=din;
		   x:='1';
		end if;
	elsif pop='1' and push='0' and cnt/=0 then--------出栈
	    if x='0' then
	      cnt:=cnt-1; -----------指针减1
          dout<=stack(cnt);------输出数据
		else
		   dout<=stack(7);
		   x:='0';
		end if;
	elsif cnt=0 then
		empty<='1';
		dout<=(others=>'0');
	end if;
end if;
full<=x;
end process;
end;