sipo.vhd

在quartus开发环境下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sipo is
port(clk:in std_logic;----时钟
     din:in std_logic;----输入数据端口
     clr:in std_logic;----清零信号
     dout:out std_logic_vector(4 downto 0));---输出数据端口
end;
architecture one of sipo is
	signal q:std_logic_vector(5 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
   if clr='1' then q<=(others=>'0');----清零
   elsif q(5)='0' then-----设置q(5)为标志位，当q(5)=0时移位结束
         q<= "11110"&din ;
   else q<= q(4 downto 0)&din ;---左移
   end if;
end if;
end process;
---------------------------
process(q)
begin
	if q(5)='0' then
	     dout<=q(4 downto 0);
	else dout<="ZZZZZ";---移位过程中的输出设置为高阻
	end if;
end process;
end;