anyodd_div.tan.rpt

在quartus开发环境下

    Info: Processing started: Tue Mar 27 21:12:59 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off anyodd_div -c anyodd_div --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 199.32 MHz between source register "cnt2[0]" and destination register "cnt2[31]" (period= 5.017 ns)
    Info: + Longest register to register delay is 4.744 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y13_N15; Fanout = 4; REG Node = 'cnt2[0]'
        Info: 2: + IC(0.657 ns) + CELL(0.596 ns) = 1.253 ns; Loc. = LCCOMB_X25_Y13_N0; Fanout = 2; COMB Node = 'Add1~385'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.339 ns; Loc. = LCCOMB_X25_Y13_N2; Fanout = 2; COMB Node = 'Add1~387'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.425 ns; Loc. = LCCOMB_X25_Y13_N4; Fanout = 2; COMB Node = 'Add1~389'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.511 ns; Loc. = LCCOMB_X25_Y13_N6; Fanout = 2; COMB Node = 'Add1~391'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.597 ns; Loc. = LCCOMB_X25_Y13_N8; Fanout = 2; COMB Node = 'Add1~393'
        Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.683 ns; Loc. = LCCOMB_X25_Y13_N10; Fanout = 2; COMB Node = 'Add1~395'
        Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.769 ns; Loc. = LCCOMB_X25_Y13_N12; Fanout = 2; COMB Node = 'Add1~397'
        Info: 9: + IC(0.000 ns) + CELL(0.190 ns) = 1.959 ns; Loc. = LCCOMB_X25_Y13_N14; Fanout = 2; COMB Node = 'Add1~399'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.045 ns; Loc. = LCCOMB_X25_Y13_N16; Fanout = 2; COMB Node = 'Add1~401'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.131 ns; Loc. = LCCOMB_X25_Y13_N18; Fanout = 2; COMB Node = 'Add1~403'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.217 ns; Loc. = LCCOMB_X25_Y13_N20; Fanout = 2; COMB Node = 'Add1~405'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.303 ns; Loc. = LCCOMB_X25_Y13_N22; Fanout = 2; COMB Node = 'Add1~407'
        Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.389 ns; Loc. = LCCOMB_X25_Y13_N24; Fanout = 2; COMB Node = 'Add1~409'
        Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.475 ns; Loc. = LCCOMB_X25_Y13_N26; Fanout = 2; COMB Node = 'Add1~411'
        Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.561 ns; Loc. = LCCOMB_X25_Y13_N28; Fanout = 2; COMB Node = 'Add1~413'
        Info: 17: + IC(0.000 ns) + CELL(0.175 ns) = 2.736 ns; Loc. = LCCOMB_X25_Y13_N30; Fanout = 2; COMB Node = 'Add1~415'
        Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.822 ns; Loc. = LCCOMB_X25_Y12_N0; Fanout = 2; COMB Node = 'Add1~417'
        Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.908 ns; Loc. = LCCOMB_X25_Y12_N2; Fanout = 2; COMB Node = 'Add1~419'
        Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 2.994 ns; Loc. = LCCOMB_X25_Y12_N4; Fanout = 2; COMB Node = 'Add1~421'
        Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.080 ns; Loc. = LCCOMB_X25_Y12_N6; Fanout = 2; COMB Node = 'Add1~423'
        Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.166 ns; Loc. = LCCOMB_X25_Y12_N8; Fanout = 2; COMB Node = 'Add1~425'
        Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.252 ns; Loc. = LCCOMB_X25_Y12_N10; Fanout = 2; COMB Node = 'Add1~427'
        Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.338 ns; Loc. = LCCOMB_X25_Y12_N12; Fanout = 2; COMB Node = 'Add1~429'
        Info: 25: + IC(0.000 ns) + CELL(0.190 ns) = 3.528 ns; Loc. = LCCOMB_X25_Y12_N14; Fanout = 2; COMB Node = 'Add1~431'
        Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.614 ns; Loc. = LCCOMB_X25_Y12_N16; Fanout = 2; COMB Node = 'Add1~433'
        Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.700 ns; Loc. = LCCOMB_X25_Y12_N18; Fanout = 2; COMB Node = 'Add1~435'
        Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.786 ns; Loc. = LCCOMB_X25_Y12_N20; Fanout = 2; COMB Node = 'Add1~437'
        Info: 29: + IC(0.000 ns) + CELL(0.086 ns) = 3.872 ns; Loc. = LCCOMB_X25_Y12_N22; Fanout = 2; COMB Node = 'Add1~439'
        Info: 30: + IC(0.000 ns) + CELL(0.086 ns) = 3.958 ns; Loc. = LCCOMB_X25_Y12_N24; Fanout = 2; COMB Node = 'Add1~441'
        Info: 31: + IC(0.000 ns) + CELL(0.086 ns) = 4.044 ns; Loc. = LCCOMB_X25_Y12_N26; Fanout = 2; COMB Node = 'Add1~443'
        Info: 32: + IC(0.000 ns) + CELL(0.086 ns) = 4.130 ns; Loc. = LCCOMB_X25_Y12_N28; Fanout = 1; COMB Node = 'Add1~445'
        Info: 33: + IC(0.000 ns) + CELL(0.506 ns) = 4.636 ns; Loc. = LCCOMB_X25_Y12_N30; Fanout = 1; COMB Node = 'Add1~446'
        Info: 34: + IC(0.000 ns) + CELL(0.108 ns) = 4.744 ns; Loc. = LCFF_X25_Y12_N31; Fanout = 2; REG Node = 'cnt2[31]'
        Info: Total cell delay = 4.087 ns ( 86.15 % )
        Info: Total interconnect delay = 0.657 ns ( 13.85 % )
    Info: - Smallest clock skew is -0.009 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.793 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 66; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X25_Y12_N31; Fanout = 2; REG Node = 'cnt2[31]'
            Info: Total cell delay = 1.756 ns ( 62.87 % )
            Info: Total interconnect delay = 1.037 ns ( 37.13 % )
        Info: - Longest clock path from clock "clk" to source register is 2.802 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 66; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.907 ns) + CELL(0.666 ns) = 2.802 ns; Loc. = LCFF_X26_Y13_N15; Fanout = 4; REG Node = 'cnt2[0]'
            Info: Total cell delay = 1.756 ns ( 62.67 % )
            Info: Total interconnect delay = 1.046 ns ( 37.33 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "clkdiv" through register "clk_temp1" is 10.406 ns
    Info: + Longest clock path from clock "clk" to source register is 2.793 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 66; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X19_Y14_N13; Fanout = 2; REG Node = 'clk_temp1'
        Info: Total cell delay = 1.756 ns ( 62.87 % )
        Info: Total interconnect delay = 1.037 ns ( 37.13 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 7.309 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y14_N13; Fanout = 2; REG Node = 'clk_temp1'
        Info: 2: + IC(2.196 ns) + CELL(0.319 ns) = 2.515 ns; Loc. = LCCOMB_X26_Y13_N4; Fanout = 1; COMB Node = 'clkdiv~0'
        Info: 3: + IC(1.758 ns) + CELL(3.036 ns) = 7.309 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'clkdiv'
        Info: Total cell delay = 3.355 ns ( 45.90 % )
        Info: Total interconnect delay = 3.954 ns ( 54.10 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Mar 27 21:13:00 2007
    Info: Elapsed time: 00:00:02