📄 reg8.tan.rpt
字号:
Timing Analyzer report for reg8
Fri Mar 16 14:51:54 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. tpd
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+---------------+---------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+---------------+---------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.603 ns ; D[5] ; 74374:inst|18 ; -- ; CLK ; 0 ;
; Worst-case tco ; N/A ; None ; 8.014 ns ; 74374:inst|18 ; Q[5] ; CLK ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 10.372 ns ; OE ; Q[5] ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.530 ns ; D[3] ; 74374:inst|16 ; -- ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+---------------+---------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+---------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+---------------+----------+
; N/A ; None ; 4.603 ns ; D[5] ; 74374:inst|18 ; CLK ;
; N/A ; None ; 4.093 ns ; D[4] ; 74374:inst|17 ; CLK ;
; N/A ; None ; 4.024 ns ; D[6] ; 74374:inst|19 ; CLK ;
; N/A ; None ; 3.650 ns ; D[7] ; 74374:inst|20 ; CLK ;
; N/A ; None ; 0.850 ns ; D[1] ; 74374:inst|14 ; CLK ;
; N/A ; None ; 0.066 ns ; D[2] ; 74374:inst|15 ; CLK ;
; N/A ; None ; -0.090 ns ; D[0] ; 74374:inst|13 ; CLK ;
; N/A ; None ; -0.264 ns ; D[3] ; 74374:inst|16 ; CLK ;
+-------+--------------+------------+------+---------------+----------+
+-----------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------------+------+------------+
; N/A ; None ; 8.014 ns ; 74374:inst|18 ; Q[5] ; CLK ;
; N/A ; None ; 7.569 ns ; 74374:inst|19 ; Q[6] ; CLK ;
; N/A ; None ; 7.560 ns ; 74374:inst|15 ; Q[2] ; CLK ;
; N/A ; None ; 7.282 ns ; 74374:inst|20 ; Q[7] ; CLK ;
; N/A ; None ; 7.264 ns ; 74374:inst|14 ; Q[1] ; CLK ;
; N/A ; None ; 7.257 ns ; 74374:inst|16 ; Q[3] ; CLK ;
; N/A ; None ; 7.163 ns ; 74374:inst|17 ; Q[4] ; CLK ;
; N/A ; None ; 7.132 ns ; 74374:inst|13 ; Q[0] ; CLK ;
+-------+--------------+------------+---------------+------+------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 10.372 ns ; OE ; Q[5] ;
; N/A ; None ; 10.360 ns ; OE ; Q[1] ;
; N/A ; None ; 10.002 ns ; OE ; Q[7] ;
; N/A ; None ; 9.982 ns ; OE ; Q[2] ;
; N/A ; None ; 9.982 ns ; OE ; Q[3] ;
; N/A ; None ; 9.982 ns ; OE ; Q[6] ;
; N/A ; None ; 9.569 ns ; OE ; Q[0] ;
; N/A ; None ; 9.541 ns ; OE ; Q[4] ;
+-------+-------------------+-----------------+------+------+
+---------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+---------------+----------+
; N/A ; None ; 0.530 ns ; D[3] ; 74374:inst|16 ; CLK ;
; N/A ; None ; 0.356 ns ; D[0] ; 74374:inst|13 ; CLK ;
; N/A ; None ; 0.200 ns ; D[2] ; 74374:inst|15 ; CLK ;
; N/A ; None ; -0.584 ns ; D[1] ; 74374:inst|14 ; CLK ;
; N/A ; None ; -3.384 ns ; D[7] ; 74374:inst|20 ; CLK ;
; N/A ; None ; -3.758 ns ; D[6] ; 74374:inst|19 ; CLK ;
; N/A ; None ; -3.827 ns ; D[4] ; 74374:inst|17 ; CLK ;
; N/A ; None ; -4.337 ns ; D[5] ; 74374:inst|18 ; CLK ;
+---------------+-------------+-----------+------+---------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Fri Mar 16 14:51:53 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off reg8 -c reg8 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: No valid register-to-register data paths exist for clock "CLK"
Info: tsu for register "74374:inst|18" (data pin = "D[5]", clock pin = "CLK") is 4.603 ns
Info: + Longest pin to register delay is 7.458 ns
Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_59; Fanout = 1; PIN Node = 'D[5]'
Info: 2: + IC(6.064 ns) + CELL(0.460 ns) = 7.458 ns; Loc. = LCFF_X22_Y1_N1; Fanout = 1; REG Node = '74374:inst|18'
Info: Total cell delay = 1.394 ns ( 18.69 % )
Info: Total interconnect delay = 6.064 ns ( 81.31 % )
Info: + Micro setup delay of destination is -0.040 ns
Info: - Shortest clock path from clock "CLK" to destination register is 2.815 ns
Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'
Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X22_Y1_N1; Fanout = 1; REG Node = '74374:inst|18'
Info: Total cell delay = 1.756 ns ( 62.38 % )
Info: Total interconnect delay = 1.059 ns ( 37.62 % )
Info: tco from clock "CLK" to destination pin "Q[5]" through register "74374:inst|18" is 8.014 ns
Info: + Longest clock path from clock "CLK" to source register is 2.815 ns
Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'
Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X22_Y1_N1; Fanout = 1; REG Node = '74374:inst|18'
Info: Total cell delay = 1.756 ns ( 62.38 % )
Info: Total interconnect delay = 1.059 ns ( 37.62 % )
Info: + Micro clock to output delay of source is 0.304 ns
Info: + Longest register to pin delay is 4.895 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y1_N1; Fanout = 1; REG Node = '74374:inst|18'
Info: 2: + IC(1.659 ns) + CELL(3.236 ns) = 4.895 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'Q[5]'
Info: Total cell delay = 3.236 ns ( 66.11 % )
Info: Total interconnect delay = 1.659 ns ( 33.89 % )
Info: Longest tpd from source pin "OE" to destination pin "Q[5]" is 10.372 ns
Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_79; Fanout = 8; PIN Node = 'OE'
Info: 2: + IC(6.119 ns) + CELL(3.318 ns) = 10.372 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'Q[5]'
Info: Total cell delay = 4.253 ns ( 41.00 % )
Info: Total interconnect delay = 6.119 ns ( 59.00 % )
Info: th for register "74374:inst|16" (data pin = "D[3]", clock pin = "CLK") is 0.530 ns
Info: + Longest clock path from clock "CLK" to destination register is 2.777 ns
Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'
Info: 3: + IC(0.882 ns) + CELL(0.666 ns) = 2.777 ns; Loc. = LCFF_X33_Y9_N1; Fanout = 1; REG Node = '74374:inst|16'
Info: Total cell delay = 1.756 ns ( 63.23 % )
Info: Total interconnect delay = 1.021 ns ( 36.77 % )
Info: + Micro hold delay of destination is 0.306 ns
Info: - Shortest pin to register delay is 2.553 ns
Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'D[3]'
Info: 2: + IC(0.983 ns) + CELL(0.460 ns) = 2.553 ns; Loc. = LCFF_X33_Y9_N1; Fanout = 1; REG Node = '74374:inst|16'
Info: Total cell delay = 1.570 ns ( 61.50 % )
Info: Total interconnect delay = 0.983 ns ( 38.50 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Fri Mar 16 14:51:54 2007
Info: Elapsed time: 00:00:03
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