div_half.map.rpt

来自「在quartus开发环境下」· RPT 代码 · 共 230 行 · 第 1/2 页

; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                 ;
+----------------------------------+-----------------+-----------------+---------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path    ;
+----------------------------------+-----------------+-----------------+---------------------------------+
; div_half.vhd                     ; yes             ; User VHDL File  ; D:/my_eda/div_half/div_half.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Estimated Total logic elements              ; 76        ;
;                                             ;           ;
; Total combinational functions               ; 76        ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 10        ;
;     -- 3 input functions                    ; 0         ;
;     -- <=2 input functions                  ; 66        ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 45        ;
;     -- arithmetic mode                      ; 31        ;
;                                             ;           ;
; Total registers                             ; 34        ;
;     -- Dedicated logic registers            ; 34        ;
;     -- I/O registers                        ; 0         ;
;                                             ;           ;
; I/O pins                                    ; 2         ;
; Maximum fan-out node                        ; clk_temp1 ;
; Maximum fan-out                             ; 33        ;
; Total fan-out                               ; 239       ;
; Average fan-out                             ; 2.13      ;
+---------------------------------------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |div_half                  ; 76 (76)           ; 34 (34)      ; 0           ; 0            ; 0       ; 0         ; 2    ; 0            ; |div_half           ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------+
; Registers Removed During Synthesis                           ;
+---------------------------------------+----------------------+
; Register name                         ; Reason for Removal   ;
+---------------------------------------+----------------------+
; clk_temp3                             ; Merged with div~reg0 ;
; Total Number of Removed Registers = 1 ;                      ;
+---------------------------------------+----------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 34    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |div_half ;
+----------------+-------+-------------------------------------------------+
; Parameter Name ; Value ; Type                                            ;
+----------------+-------+-------------------------------------------------+
; n              ; 2     ; Signed Integer                                  ;
+----------------+-------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat Mar 31 21:22:28 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off div_half -c div_half
Info: Found 2 design units, including 1 entities, in source file div_half.vhd
    Info: Found design unit 1: div_half-one
    Info: Found entity 1: div_half
Info: Elaborating entity "div_half" for the top level hierarchy
Info: Duplicate registers merged to single register
    Info: Duplicate register "clk_temp3" merged to single register "div~reg0"
Info: Implemented 79 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 77 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 133 megabytes of memory during processing
    Info: Processing ended: Sat Mar 31 21:22:31 2007
    Info: Elapsed time: 00:00:03