bcd_decoder.tan.rpt

来自「在quartus开发环境下」· RPT 代码 · 共 127 行

Timing Analyzer report for bcd_decoder
Mon Mar 05 22:15:33 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 13.056 ns   ; i[2] ; y[0] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;      ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 13.056 ns       ; i[2] ; y[0] ;
; N/A   ; None              ; 13.007 ns       ; i[2] ; y[1] ;
; N/A   ; None              ; 12.936 ns       ; i[1] ; y[0] ;
; N/A   ; None              ; 12.927 ns       ; i[1] ; y[1] ;
; N/A   ; None              ; 12.663 ns       ; i[3] ; y[1] ;
; N/A   ; None              ; 12.649 ns       ; i[3] ; y[0] ;
; N/A   ; None              ; 12.620 ns       ; i[2] ; y[3] ;
; N/A   ; None              ; 12.597 ns       ; i[2] ; y[4] ;
; N/A   ; None              ; 12.592 ns       ; i[2] ; y[5] ;
; N/A   ; None              ; 12.588 ns       ; i[2] ; y[6] ;
; N/A   ; None              ; 12.582 ns       ; i[2] ; y[2] ;
; N/A   ; None              ; 12.567 ns       ; i[0] ; y[1] ;
; N/A   ; None              ; 12.564 ns       ; i[0] ; y[0] ;
; N/A   ; None              ; 12.511 ns       ; i[1] ; y[3] ;
; N/A   ; None              ; 12.475 ns       ; i[1] ; y[4] ;
; N/A   ; None              ; 12.472 ns       ; i[1] ; y[5] ;
; N/A   ; None              ; 12.438 ns       ; i[1] ; y[6] ;
; N/A   ; None              ; 12.425 ns       ; i[1] ; y[2] ;
; N/A   ; None              ; 12.250 ns       ; i[3] ; y[3] ;
; N/A   ; None              ; 12.218 ns       ; i[3] ; y[6] ;
; N/A   ; None              ; 12.209 ns       ; i[3] ; y[4] ;
; N/A   ; None              ; 12.205 ns       ; i[3] ; y[2] ;
; N/A   ; None              ; 12.191 ns       ; i[3] ; y[5] ;
; N/A   ; None              ; 12.151 ns       ; i[0] ; y[3] ;
; N/A   ; None              ; 12.120 ns       ; i[0] ; y[6] ;
; N/A   ; None              ; 12.112 ns       ; i[0] ; y[4] ;
; N/A   ; None              ; 12.107 ns       ; i[0] ; y[2] ;
; N/A   ; None              ; 12.100 ns       ; i[0] ; y[5] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Mar 05 22:15:33 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bcd_decoder -c bcd_decoder --timing_analysis_only
Info: Longest tpd from source pin "i[2]" to destination pin "y[0]" is 13.056 ns
    Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 7; PIN Node = 'i[2]'
    Info: 2: + IC(6.971 ns) + CELL(0.624 ns) = 8.529 ns; Loc. = LCCOMB_X33_Y18_N16; Fanout = 1; COMB Node = 'Mux6~3'
    Info: 3: + IC(1.481 ns) + CELL(3.046 ns) = 13.056 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'y[0]'
    Info: Total cell delay = 4.604 ns ( 35.26 % )
    Info: Total interconnect delay = 8.452 ns ( 64.74 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Mar 05 22:15:33 2007
    Info: Elapsed time: 00:00:02