jk.map.rpt

在quartus开发环境下

; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; Jk.vhd                           ; yes             ; User VHDL File  ; D:/my_eda/Jk/Jk.vhd          ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 10    ;
;                                             ;       ;
; Total combinational functions               ; 10    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 5     ;
;     -- 3 input functions                    ; 2     ;
;     -- <=2 input functions                  ; 3     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 10    ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 2     ;
;     -- Dedicated logic registers            ; 2     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 7     ;
; Maximum fan-out node                        ; r     ;
; Maximum fan-out                             ; 6     ;
; Total fan-out                               ; 42    ;
; Average fan-out                             ; 2.21  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |JK                        ; 10 (10)           ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 7    ; 0            ; |JK                 ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 2     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 2     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 2     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |JK|q_temp                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun May 27 20:53:12 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Jk -c Jk
Info: Found 2 design units, including 1 entities, in source file Jk.vhd
    Info: Found design unit 1: Jk-one
    Info: Found entity 1: JK
Info: Elaborating entity "Jk" for the top level hierarchy
Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state.
    Info: Register "q_temp" converted into equivalent circuit using register "q_temp~_emulated" and latch "q_temp~34"
    Info: Register "qn_temp" converted into equivalent circuit using register "qn_temp~_emulated" and latch "qn_temp~24"
Info: Implemented 17 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 2 output pins
    Info: Implemented 10 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 142 megabytes of memory during processing
    Info: Processing ended: Sun May 27 20:53:17 2007
    Info: Elapsed time: 00:00:05