jk.tan.rpt

在quartus开发环境下

+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 12.055 ns       ; s    ; q  ;
; N/A   ; None              ; 11.751 ns       ; r    ; q  ;
; N/A   ; None              ; 11.723 ns       ; s    ; qn ;
; N/A   ; None              ; 11.419 ns       ; r    ; qn ;
+-------+-------------------+-----------------+------+----+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; 0.902 ns  ; j    ; q_temp~_emulated  ; cp       ;
; N/A           ; None        ; 0.901 ns  ; j    ; qn_temp~_emulated ; cp       ;
; N/A           ; None        ; 0.703 ns  ; k    ; q_temp~_emulated  ; cp       ;
; N/A           ; None        ; 0.703 ns  ; k    ; qn_temp~_emulated ; cp       ;
; N/A           ; None        ; -4.929 ns ; r    ; qn_temp~_emulated ; cp       ;
; N/A           ; None        ; -4.930 ns ; r    ; q_temp~_emulated  ; cp       ;
; N/A           ; None        ; -5.233 ns ; s    ; qn_temp~_emulated ; cp       ;
; N/A           ; None        ; -5.234 ns ; s    ; q_temp~_emulated  ; cp       ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun May 27 20:54:03 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Jk -c Jk --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "q_temp~34" is a latch
    Warning: Node "qn_temp~24" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "cp" is an undefined clock
Info: Clock "cp" Internal fmax is restricted to 340.02 MHz between source register "q_temp~_emulated" and destination register "q_temp~_emulated"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.333 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
            Info: 2: + IC(0.437 ns) + CELL(0.206 ns) = 0.643 ns; Loc. = LCCOMB_X1_Y9_N18; Fanout = 2; COMB Node = 'q_temp~260'
            Info: 3: + IC(0.376 ns) + CELL(0.206 ns) = 1.225 ns; Loc. = LCCOMB_X1_Y9_N6; Fanout = 1; COMB Node = 'q_temp~261'
            Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.333 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
            Info: Total cell delay = 0.520 ns ( 39.01 % )
            Info: Total interconnect delay = 0.813 ns ( 60.99 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "cp" to destination register is 2.766 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'
                Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
                Info: Total cell delay = 1.756 ns ( 63.49 % )
                Info: Total interconnect delay = 1.010 ns ( 36.51 % )
            Info: - Longest clock path from clock "cp" to source register is 2.766 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'
                Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
                Info: Total cell delay = 1.756 ns ( 63.49 % )
                Info: Total interconnect delay = 1.010 ns ( 36.51 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q_temp~_emulated" (data pin = "s", clock pin = "cp") is 6.233 ns
    Info: + Longest pin to register delay is 9.039 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_142; Fanout = 6; PIN Node = 's'
        Info: 2: + IC(6.300 ns) + CELL(0.624 ns) = 7.868 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 2; COMB Node = 'q_temp~263'
        Info: 3: + IC(0.316 ns) + CELL(0.855 ns) = 9.039 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
        Info: Total cell delay = 2.423 ns ( 26.81 % )
        Info: Total interconnect delay = 6.616 ns ( 73.19 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "cp" to destination register is 2.766 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'
        Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
        Info: Total cell delay = 1.756 ns ( 63.49 % )
        Info: Total interconnect delay = 1.010 ns ( 36.51 % )
Info: tco from clock "cp" to destination pin "q" through register "q_temp~_emulated" is 8.152 ns
    Info: + Longest clock path from clock "cp" to source register is 2.766 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'
        Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
        Info: Total cell delay = 1.756 ns ( 63.49 % )
        Info: Total interconnect delay = 1.010 ns ( 36.51 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.082 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
        Info: 2: + IC(0.437 ns) + CELL(0.206 ns) = 0.643 ns; Loc. = LCCOMB_X1_Y9_N18; Fanout = 2; COMB Node = 'q_temp~260'
        Info: 3: + IC(1.383 ns) + CELL(3.056 ns) = 5.082 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 3.262 ns ( 64.19 % )
        Info: Total interconnect delay = 1.820 ns ( 35.81 % )
Info: Longest tpd from source pin "s" to destination pin "q" is 12.055 ns
    Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_142; Fanout = 6; PIN Node = 's'
    Info: 2: + IC(6.302 ns) + CELL(0.370 ns) = 7.616 ns; Loc. = LCCOMB_X1_Y9_N18; Fanout = 2; COMB Node = 'q_temp~260'
    Info: 3: + IC(1.383 ns) + CELL(3.056 ns) = 12.055 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'q'
    Info: Total cell delay = 4.370 ns ( 36.25 % )
    Info: Total interconnect delay = 7.685 ns ( 63.75 % )
Info: th for register "q_temp~_emulated" (data pin = "j", clock pin = "cp") is 0.902 ns
    Info: + Longest clock path from clock "cp" to destination register is 2.766 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'cp'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'cp~clkctrl'
        Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.766 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
        Info: Total cell delay = 1.756 ns ( 63.49 % )
        Info: Total interconnect delay = 1.010 ns ( 36.51 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 2.170 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_21; Fanout = 3; PIN Node = 'j'
        Info: 2: + IC(0.602 ns) + CELL(0.370 ns) = 2.062 ns; Loc. = LCCOMB_X1_Y9_N6; Fanout = 1; COMB Node = 'q_temp~261'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.170 ns; Loc. = LCFF_X1_Y9_N7; Fanout = 1; REG Node = 'q_temp~_emulated'
        Info: Total cell delay = 1.568 ns ( 72.26 % )
        Info: Total interconnect delay = 0.602 ns ( 27.74 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Sun May 27 20:54:05 2007
    Info: Elapsed time: 00:00:02