div5_1.tan.qmsg

来自「在quartus开发环境下」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk div5 div5~reg0 8.865 ns register " "Info: tco from clock \"clk\" to destination pin \"div5\" through register \"div5~reg0\" is 8.865 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.924 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.787 ns) 2.600 ns cnt2\[0\] 3 REG LCFF_X4_Y4_N27 4 " "Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X4_Y4_N27; Fanout = 4; REG Node = 'cnt2\[0\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl cnt2[0] } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.275 ns) 3.626 ns out_temp~68 4 COMB LCCOMB_X4_Y3_N20 1 " "Info: 4: + IC(0.751 ns) + CELL(0.275 ns) = 3.626 ns; Loc. = LCCOMB_X4_Y3_N20; Fanout = 1; COMB Node = 'out_temp~68'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.026 ns" { cnt2[0] out_temp~68 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.249 ns) + CELL(0.275 ns) 4.150 ns out_temp~69 5 COMB LCCOMB_X4_Y3_N8 1 " "Info: 5: + IC(0.249 ns) + CELL(0.275 ns) = 4.150 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.524 ns" { out_temp~68 out_temp~69 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.237 ns) + CELL(0.537 ns) 4.924 ns div5~reg0 6 REG LCFF_X4_Y3_N19 2 " "Info: 6: + IC(0.237 ns) + CELL(0.537 ns) = 4.924 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.774 ns" { out_temp~69 div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.863 ns ( 58.14 % ) " "Info: Total cell delay = 2.863 ns ( 58.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.061 ns ( 41.86 % ) " "Info: Total interconnect delay = 2.061 ns ( 41.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.924 ns" { clk clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.924 ns" { clk clk~combout clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns 0.751ns 0.249ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.275ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.691 ns + Longest register pin " "Info: + Longest register to pin delay is 3.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div5~reg0 1 REG LCFF_X4_Y3_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(2.798 ns) 3.691 ns div5 2 PIN PIN_52 0 " "Info: 2: + IC(0.893 ns) + CELL(2.798 ns) = 3.691 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'div5'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.691 ns" { div5~reg0 div5 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 75.81 % ) " "Info: Total cell delay = 2.798 ns ( 75.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.893 ns ( 24.19 % ) " "Info: Total interconnect delay = 0.893 ns ( 24.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.691 ns" { div5~reg0 div5 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.691 ns" { div5~reg0 div5 } { 0.000ns 0.893ns } { 0.000ns 2.798ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.924 ns" { clk clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.924 ns" { clk clk~combout clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns 0.751ns 0.249ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.275ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.691 ns" { div5~reg0 div5 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.691 ns" { div5~reg0 div5 } { 0.000ns 0.893ns } { 0.000ns 2.798ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 28 15:44:32 2007 " "Info: Processing ended: Wed Mar 28 15:44:32 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}