div5_1.tan.rpt

来自「在quartus开发环境下」· RPT 代码 · 共 223 行 · 第 1/2 页

+------------------------------------------+-----------+-----------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From      ; To        ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+-----------+-----------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; div5~reg0 ; div5~reg0 ; clk        ; clk      ; None                       ; None                       ; 0.407 ns                 ;
+------------------------------------------+-----------+-----------+------------+----------+----------------------------+----------------------------+--------------------------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 8.865 ns   ; div5~reg0 ; div5 ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Mar 28 15:44:32 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div5_1 -c div5_1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "cnt2[1]" as buffer
    Info: Detected ripple clock "cnt2[0]" as buffer
    Info: Detected ripple clock "cnt1[1]" as buffer
    Info: Detected ripple clock "cnt1[2]" as buffer
    Info: Detected gated clock "out_temp~68" as buffer
    Info: Detected ripple clock "cnt1[0]" as buffer
    Info: Detected ripple clock "cnt2[2]" as buffer
    Info: Detected gated clock "out_temp~69" as buffer
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "div5~reg0" and destination register "div5~reg0"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.407 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
            Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X4_Y3_N18; Fanout = 1; COMB Node = 'div5~4'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
            Info: Total cell delay = 0.407 ns ( 100.00 % )
        Info: - Smallest clock skew is -1.090 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.834 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.705 ns) + CELL(0.787 ns) = 2.603 ns; Loc. = LCFF_X4_Y3_N23; Fanout = 3; REG Node = 'cnt1[2]'
                Info: 4: + IC(0.307 ns) + CELL(0.150 ns) = 3.060 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'
                Info: 5: + IC(0.237 ns) + CELL(0.537 ns) = 3.834 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
                Info: Total cell delay = 2.463 ns ( 64.24 % )
                Info: Total interconnect delay = 1.371 ns ( 35.76 % )
            Info: - Longest clock path from clock "clk" to source register is 4.924 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X4_Y4_N27; Fanout = 4; REG Node = 'cnt2[0]'
                Info: 4: + IC(0.751 ns) + CELL(0.275 ns) = 3.626 ns; Loc. = LCCOMB_X4_Y3_N20; Fanout = 1; COMB Node = 'out_temp~68'
                Info: 5: + IC(0.249 ns) + CELL(0.275 ns) = 4.150 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'
                Info: 6: + IC(0.237 ns) + CELL(0.537 ns) = 4.924 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
                Info: Total cell delay = 2.863 ns ( 58.14 % )
                Info: Total interconnect delay = 2.061 ns ( 41.86 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "div5~reg0" and destination pin or register "div5~reg0" for clock "clk" (Hold time is 699 ps)
    Info: + Largest clock skew is 1.090 ns
        Info: + Longest clock path from clock "clk" to destination register is 4.924 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X4_Y4_N27; Fanout = 4; REG Node = 'cnt2[0]'
            Info: 4: + IC(0.751 ns) + CELL(0.275 ns) = 3.626 ns; Loc. = LCCOMB_X4_Y3_N20; Fanout = 1; COMB Node = 'out_temp~68'
            Info: 5: + IC(0.249 ns) + CELL(0.275 ns) = 4.150 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'
            Info: 6: + IC(0.237 ns) + CELL(0.537 ns) = 4.924 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
            Info: Total cell delay = 2.863 ns ( 58.14 % )
            Info: Total interconnect delay = 2.061 ns ( 41.86 % )
        Info: - Shortest clock path from clock "clk" to source register is 3.834 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.705 ns) + CELL(0.787 ns) = 2.603 ns; Loc. = LCFF_X4_Y3_N23; Fanout = 3; REG Node = 'cnt1[2]'
            Info: 4: + IC(0.307 ns) + CELL(0.150 ns) = 3.060 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'
            Info: 5: + IC(0.237 ns) + CELL(0.537 ns) = 3.834 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
            Info: Total cell delay = 2.463 ns ( 64.24 % )
            Info: Total interconnect delay = 1.371 ns ( 35.76 % )
    Info: - Micro clock to output delay of source is 0.250 ns
    Info: - Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X4_Y3_N18; Fanout = 1; COMB Node = 'div5~4'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 0.266 ns
Info: tco from clock "clk" to destination pin "div5" through register "div5~reg0" is 8.865 ns
    Info: + Longest clock path from clock "clk" to source register is 4.924 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X4_Y4_N27; Fanout = 4; REG Node = 'cnt2[0]'
        Info: 4: + IC(0.751 ns) + CELL(0.275 ns) = 3.626 ns; Loc. = LCCOMB_X4_Y3_N20; Fanout = 1; COMB Node = 'out_temp~68'
        Info: 5: + IC(0.249 ns) + CELL(0.275 ns) = 4.150 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'
        Info: 6: + IC(0.237 ns) + CELL(0.537 ns) = 4.924 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
        Info: Total cell delay = 2.863 ns ( 58.14 % )
        Info: Total interconnect delay = 2.061 ns ( 41.86 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.691 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'
        Info: 2: + IC(0.893 ns) + CELL(2.798 ns) = 3.691 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'div5'
        Info: Total cell delay = 2.798 ns ( 75.81 % )
        Info: Total interconnect delay = 0.893 ns ( 24.19 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Wed Mar 28 15:44:32 2007
    Info: Elapsed time: 00:00:02