xl_generate.tan.rpt

来自「在quartus开发环境下」· RPT 代码 · 共 227 行 · 第 1/2 页

; N/A   ; None         ; 4.052 ns   ; clr  ; dout~reg0 ; clk      ;
; N/A   ; None         ; 4.051 ns   ; clr  ; reg[1]    ; clk      ;
; N/A   ; None         ; 4.050 ns   ; clr  ; reg[6]    ; clk      ;
; N/A   ; None         ; 4.047 ns   ; clr  ; reg[3]    ; clk      ;
+-------+--------------+------------+------+-----------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 6.814 ns   ; dout~reg0 ; dout ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -3.781 ns ; clr  ; reg[3]    ; clk      ;
; N/A           ; None        ; -3.784 ns ; clr  ; reg[6]    ; clk      ;
; N/A           ; None        ; -3.785 ns ; clr  ; reg[1]    ; clk      ;
; N/A           ; None        ; -3.786 ns ; clr  ; dout~reg0 ; clk      ;
; N/A           ; None        ; -3.935 ns ; clr  ; reg[4]    ; clk      ;
; N/A           ; None        ; -3.936 ns ; clr  ; reg[7]    ; clk      ;
; N/A           ; None        ; -3.936 ns ; clr  ; reg[5]    ; clk      ;
; N/A           ; None        ; -3.937 ns ; clr  ; reg[2]    ; clk      ;
; N/A           ; None        ; -3.937 ns ; clr  ; reg[0]    ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sun Mar 25 22:40:05 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off xl_generate -c xl_generate --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "reg[7]" and destination register "dout~reg0"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.757 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y11_N3; Fanout = 2; REG Node = 'reg[7]'
            Info: 2: + IC(0.443 ns) + CELL(0.206 ns) = 0.649 ns; Loc. = LCCOMB_X1_Y11_N16; Fanout = 1; COMB Node = 'dout~15'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.757 ns; Loc. = LCFF_X1_Y11_N17; Fanout = 1; REG Node = 'dout~reg0'
            Info: Total cell delay = 0.314 ns ( 41.48 % )
            Info: Total interconnect delay = 0.443 ns ( 58.52 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.750 ns
                Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.750 ns; Loc. = LCFF_X1_Y11_N17; Fanout = 1; REG Node = 'dout~reg0'
                Info: Total cell delay = 1.766 ns ( 64.22 % )
                Info: Total interconnect delay = 0.984 ns ( 35.78 % )
            Info: - Longest clock path from clock "clk" to source register is 2.750 ns
                Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.750 ns; Loc. = LCFF_X1_Y11_N3; Fanout = 2; REG Node = 'reg[7]'
                Info: Total cell delay = 1.766 ns ( 64.22 % )
                Info: Total interconnect delay = 0.984 ns ( 35.78 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "reg[2]" (data pin = "clr", clock pin = "clk") is 4.203 ns
    Info: + Longest pin to register delay is 6.993 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_7; Fanout = 9; PIN Node = 'clr'
        Info: 2: + IC(5.289 ns) + CELL(0.651 ns) = 6.885 ns; Loc. = LCCOMB_X1_Y11_N22; Fanout = 1; COMB Node = 'reg~109'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.993 ns; Loc. = LCFF_X1_Y11_N23; Fanout = 1; REG Node = 'reg[2]'
        Info: Total cell delay = 1.704 ns ( 24.37 % )
        Info: Total interconnect delay = 5.289 ns ( 75.63 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.750 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.750 ns; Loc. = LCFF_X1_Y11_N23; Fanout = 1; REG Node = 'reg[2]'
        Info: Total cell delay = 1.766 ns ( 64.22 % )
        Info: Total interconnect delay = 0.984 ns ( 35.78 % )
Info: tco from clock "clk" to destination pin "dout" through register "dout~reg0" is 6.814 ns
    Info: + Longest clock path from clock "clk" to source register is 2.750 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.750 ns; Loc. = LCFF_X1_Y11_N17; Fanout = 1; REG Node = 'dout~reg0'
        Info: Total cell delay = 1.766 ns ( 64.22 % )
        Info: Total interconnect delay = 0.984 ns ( 35.78 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 3.760 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y11_N17; Fanout = 1; REG Node = 'dout~reg0'
        Info: 2: + IC(0.704 ns) + CELL(3.056 ns) = 3.760 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'dout'
        Info: Total cell delay = 3.056 ns ( 81.28 % )
        Info: Total interconnect delay = 0.704 ns ( 18.72 % )
Info: th for register "reg[3]" (data pin = "clr", clock pin = "clk") is -3.781 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.750 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.243 ns; Loc. = CLKCTRL_G2; Fanout = 9; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.841 ns) + CELL(0.666 ns) = 2.750 ns; Loc. = LCFF_X1_Y11_N13; Fanout = 1; REG Node = 'reg[3]'
        Info: Total cell delay = 1.766 ns ( 64.22 % )
        Info: Total interconnect delay = 0.984 ns ( 35.78 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 6.837 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_7; Fanout = 9; PIN Node = 'clr'
        Info: 2: + IC(5.285 ns) + CELL(0.499 ns) = 6.729 ns; Loc. = LCCOMB_X1_Y11_N12; Fanout = 1; COMB Node = 'reg~108'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.837 ns; Loc. = LCFF_X1_Y11_N13; Fanout = 1; REG Node = 'reg[3]'
        Info: Total cell delay = 1.552 ns ( 22.70 % )
        Info: Total interconnect delay = 5.285 ns ( 77.30 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Mar 25 22:40:06 2007
    Info: Elapsed time: 00:00:02