reg8_1.vhd

来自「在quartus开发环境下」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg8_1 is
port(d:in std_logic_vector(7 downto 0);  ----数据输入
     oe:in std_logic;                    ----三态控制端口
     clk:in std_logic;                   ----时钟输入
     q:out std_logic_vector(7 downto 0));----数据输出
end;
architecture one of reg8_1 is
signal q_temp:std_logic_vector(7 downto 0);
begin
process(clk,oe)
begin
if oe='0' then
	if clk'event and clk='1' then
	q_temp<=d;
	end if;
else q_temp<="ZZZZZZZZ";
end if;
end process;
q<=q_temp;
end;