tri_gate_1.vhd

来自「在quartus开发环境下」· VHDL 代码 · 共 15 行

library ieee;
use ieee.std_logic_1164.all;
entity tri_gate_1 is
port(din,en:in std_logic;
     dout:out std_logic);
end;
architecture one of tri_gate_1 is
begin
process(din,en)
begin
	if en='1' then dout<=din;
	else dout<='Z';
	end if;
end process;
end;