t.tan.qmsg

在quartus开发环境下

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "cp register register q_temp q_temp 360.1 MHz Internal " "Info: Clock \"cp\" Internal fmax is restricted to 360.1 MHz between source register \"q_temp\" and destination register \"q_temp\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Longest register register " "Info: + Longest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_temp 1 REG LCFF_X8_Y16_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns q_temp~5 2 COMB LCCOMB_X8_Y16_N16 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X8_Y16_N16; Fanout = 1; COMB Node = 'q_temp~5'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { q_temp q_temp~5 } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns q_temp 3 REG LCFF_X8_Y16_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { q_temp~5 q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { q_temp q_temp~5 q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { q_temp q_temp~5 q_temp } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.949 ns + Shortest register " "Info: + Shortest clock path from clock \"cp\" to destination register is 2.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.666 ns) 2.949 ns q_temp 2 REG LCFF_X8_Y16_N17 2 " "Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.015 ns" { cp q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.26 % ) " "Info: Total cell delay = 1.600 ns ( 54.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.349 ns ( 45.74 % ) " "Info: Total interconnect delay = 1.349 ns ( 45.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.949 ns - Longest register " "Info: - Longest clock path from clock \"cp\" to source register is 2.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.666 ns) 2.949 ns q_temp 2 REG LCFF_X8_Y16_N17 2 " "Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.015 ns" { cp q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.26 % ) " "Info: Total cell delay = 1.600 ns ( 54.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.349 ns ( 45.74 % ) " "Info: Total interconnect delay = 1.349 ns ( 45.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { q_temp q_temp~5 q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { q_temp q_temp~5 q_temp } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { q_temp } {  } {  } "" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q_temp t cp 4.596 ns register " "Info: tsu for register \"q_temp\" (data pin = \"t\", clock pin = \"cp\") is 4.596 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.585 ns + Longest pin register " "Info: + Longest pin to register delay is 7.585 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns t 1 PIN PIN_51 1 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 't'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { t } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.327 ns) + CELL(0.206 ns) 7.477 ns q_temp~5 2 COMB LCCOMB_X8_Y16_N16 1 " "Info: 2: + IC(6.327 ns) + CELL(0.206 ns) = 7.477 ns; Loc. = LCCOMB_X8_Y16_N16; Fanout = 1; COMB Node = 'q_temp~5'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.533 ns" { t q_temp~5 } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.585 ns q_temp 3 REG LCFF_X8_Y16_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.585 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { q_temp~5 q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.258 ns ( 16.59 % ) " "Info: Total cell delay = 1.258 ns ( 16.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.327 ns ( 83.41 % ) " "Info: Total interconnect delay = 6.327 ns ( 83.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.585 ns" { t q_temp~5 q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.585 ns" { t t~combout q_temp~5 q_temp } { 0.000ns 0.000ns 6.327ns 0.000ns } { 0.000ns 0.944ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.949 ns - Shortest register " "Info: - Shortest clock path from clock \"cp\" to destination register is 2.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.666 ns) 2.949 ns q_temp 2 REG LCFF_X8_Y16_N17 2 " "Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.015 ns" { cp q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.26 % ) " "Info: Total cell delay = 1.600 ns ( 54.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.349 ns ( 45.74 % ) " "Info: Total interconnect delay = 1.349 ns ( 45.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.585 ns" { t q_temp~5 q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.585 ns" { t t~combout q_temp~5 q_temp } { 0.000ns 0.000ns 6.327ns 0.000ns } { 0.000ns 0.944ns 0.206ns 0.108ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cp q q_temp 7.689 ns register " "Info: tco from clock \"cp\" to destination pin \"q\" through register \"q_temp\" is 7.689 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp source 2.949 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to source register is 2.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.666 ns) 2.949 ns q_temp 2 REG LCFF_X8_Y16_N17 2 " "Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.015 ns" { cp q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.26 % ) " "Info: Total cell delay = 1.600 ns ( 54.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.349 ns ( 45.74 % ) " "Info: Total interconnect delay = 1.349 ns ( 45.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.436 ns + Longest register pin " "Info: + Longest register to pin delay is 4.436 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_temp 1 REG LCFF_X8_Y16_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.390 ns) + CELL(3.046 ns) 4.436 ns q 2 PIN PIN_7 0 " "Info: 2: + IC(1.390 ns) + CELL(3.046 ns) = 4.436 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'q'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.436 ns" { q_temp q } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.046 ns ( 68.67 % ) " "Info: Total cell delay = 3.046 ns ( 68.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.390 ns ( 31.33 % ) " "Info: Total interconnect delay = 1.390 ns ( 31.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.436 ns" { q_temp q } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.436 ns" { q_temp q } { 0.000ns 1.390ns } { 0.000ns 3.046ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.436 ns" { q_temp q } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.436 ns" { q_temp q } { 0.000ns 1.390ns } { 0.000ns 3.046ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q_temp t cp -4.330 ns register " "Info: th for register \"q_temp\" (data pin = \"t\", clock pin = \"cp\") is -4.330 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp destination 2.949 ns + Longest register " "Info: + Longest clock path from clock \"cp\" to destination register is 2.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns cp 1 CLK PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'cp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.666 ns) 2.949 ns q_temp 2 REG LCFF_X8_Y16_N17 2 " "Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.949 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.015 ns" { cp q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 54.26 % ) " "Info: Total cell delay = 1.600 ns ( 54.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.349 ns ( 45.74 % ) " "Info: Total interconnect delay = 1.349 ns ( 45.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.585 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.585 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns t 1 PIN PIN_51 1 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 't'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { t } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.327 ns) + CELL(0.206 ns) 7.477 ns q_temp~5 2 COMB LCCOMB_X8_Y16_N16 1 " "Info: 2: + IC(6.327 ns) + CELL(0.206 ns) = 7.477 ns; Loc. = LCCOMB_X8_Y16_N16; Fanout = 1; COMB Node = 'q_temp~5'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.533 ns" { t q_temp~5 } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.585 ns q_temp 3 REG LCFF_X8_Y16_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.585 ns; Loc. = LCFF_X8_Y16_N17; Fanout = 2; REG Node = 'q_temp'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { q_temp~5 q_temp } "NODE_NAME" } } { "T.vhd" "" { Text "D:/my_eda/T/T.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.258 ns ( 16.59 % ) " "Info: Total cell delay = 1.258 ns ( 16.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.327 ns ( 83.41 % ) " "Info: Total interconnect delay = 6.327 ns ( 83.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.585 ns" { t q_temp~5 q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.585 ns" { t t~combout q_temp~5 q_temp } { 0.000ns 0.000ns 6.327ns 0.000ns } { 0.000ns 0.944ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.949 ns" { cp q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.949 ns" { cp cp~combout q_temp } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.934ns 0.666ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.585 ns" { t q_temp~5 q_temp } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.585 ns" { t t~combout q_temp~5 q_temp } { 0.000ns 0.000ns 6.327ns 0.000ns } { 0.000ns 0.944ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 27 21:18:12 2007 " "Info: Processing ended: Sun May 27 21:18:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}