t.vhd

在quartus开发环境下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity t is
port(t,cp:in std_logic;
     q:out std_logic);
end;
architecture one of t is
	signal q_temp:std_logic;
begin
process(cp)
begin
if cp'event and cp='1' then
	if t='1' then
		q_temp<=not q_temp;
	else
		q_temp<=q_temp;
	end if;
end if;
end process;
q<=q_temp;
end;