📄 t.fit.rpt
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; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; -3655 ;
; Internal Atom Count - Fit Attempt 1 ; 3 ;
; LE/ALM Count - Fit Attempt 1 ; 2 ;
; LAB Count - Fit Attempt 1 ; 2 ;
; Outputs per Lab - Fit Attempt 1 ; 0.500 ;
; Inputs per LAB - Fit Attempt 1 ; 1.000 ;
; Global Inputs per LAB - Fit Attempt 1 ; 0.000 ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1 ; 0:1;1:1 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:1;1:1 ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1 ; 0:1;1:1 ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'global controls' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:1;1:1 ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:1;1:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:1;1:1 ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1 ; 0:1;1:1 ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1 ; 0:2 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:2 ;
; LEs in Chains - Fit Attempt 1 ; 0 ;
; LEs in Long Chains - Fit Attempt 1 ; 0 ;
; LABs with Chains - Fit Attempt 1 ; 0 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
+------------------------------------------------------------------+---------+
+---------------------------------------------+
; Advanced Data - Placement ;
+-------------------------------------+-------+
; Name ; Value ;
+-------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Early Slack - Fit Attempt 1 ; -1325 ;
; Auto Fit Point 3 - Fit Attempt 1 ; ff ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 0 ;
; Mid Slack - Fit Attempt 1 ; -1325 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Late Slack - Fit Attempt 1 ; -1325 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
+-------------------------------------+-------+
+---------------------------------------------+
; Advanced Data - Routing ;
+-------------------------------------+-------+
; Name ; Value ;
+-------------------------------------+-------+
; Early Wire Use - Fit Attempt 1 ; 0 ;
; Peak Regional Wire - Fit Attempt 1 ; 0 ;
; Early Slack - Fit Attempt 1 ; -64 ;
; Mid Slack - Fit Attempt 1 ; -64 ;
; Late Slack - Fit Attempt 1 ; -64 ;
; Late Wire Use - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.032 ;
+-------------------------------------+-------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Sun May 27 21:10:19 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off T -c T
Info: Selected device EP2C8T144C8 for design "T"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP2C5T144C8 is compatible
Info: Device EP2C5T144I8 is compatible
Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location 1
Info: Pin ~nCSO~ is reserved at location 2
Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 3 pins of 3 total pins
Info: Pin q not assigned to an exact location on the device
Info: Pin t not assigned to an exact location on the device
Info: Pin cp not assigned to an exact location on the device
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 3 (unused VREF, 3.30 VCCIO, 2 input, 1 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used -- 15 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 23 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 20 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 0.812 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y16; Fanout = 2; REG Node = 'q_temp'
Info: 2: + IC(0.334 ns) + CELL(0.370 ns) = 0.704 ns; Loc. = LAB_X8_Y16; Fanout = 1; COMB Node = 'q_temp~5'
Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.812 ns; Loc. = LAB_X8_Y16; Fanout = 2; REG Node = 'q_temp'
Info: Total cell delay = 0.478 ns ( 58.87 % )
Info: Total interconnect delay = 0.334 ns ( 41.13 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
Info: The peak interconnect region extends from location X0_Y10 to location X10_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 1 output pins without output pin load capacitance assignment
Info: Pin "q" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
Info: Allocated 175 megabytes of memory during processing
Info: Processing ended: Sun May 27 21:10:29 2007
Info: Elapsed time: 00:00:10
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/my_eda/T/T.fit.smsg.
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